From c8d47169f43da95fcf8a8c385d49e0a464e58a97 Mon Sep 17 00:00:00 2001 From: Lean Sheng Tan Date: Thu, 7 Mar 2024 17:46:25 +0100 Subject: soc/intel/alderlake: Add Raptor Lake System Agent Device IDs Add System Agent IDs for Raptor Lake SKUs based on RPL Datasheet (Doc ID: 743844) & EDS Vol 1 (Doc ID: 640555). Signed-off-by: Lean Sheng Tan Change-Id: I805040c65852742f1bbc43b443e115bcb0a930aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/81115 Reviewed-by: Jan Samek Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 3 +++ src/soc/intel/alderlake/bootblock/report_platform.c | 13 ++++++++----- src/soc/intel/alderlake/chip.h | 3 +++ src/soc/intel/alderlake/cpu.c | 3 +++ src/soc/intel/alderlake/fsp_params.c | 3 +++ src/soc/intel/alderlake/vr_config.c | 12 ++++++++++++ src/soc/intel/common/block/systemagent/systemagent.c | 3 +++ 7 files changed, 35 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f980f4e14f..1ae09f0555 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4285,6 +4285,9 @@ #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 #define PCI_DID_INTEL_RPL_P_ID_4 0xa71b #define PCI_DID_INTEL_RPL_P_ID_5 0xa71c +#define PCI_DID_INTEL_RPL_P_ID_6 0xa709 +#define PCI_DID_INTEL_RPL_P_ID_7 0xa70a +#define PCI_DID_INTEL_RPL_P_ID_8 0xa716 #define PCI_DID_INTEL_LNL_M_ID 0x6400 /* Intel SMBUS device Ids */ diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2a4f31a0d1..bd4960d0fe 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -84,11 +84,14 @@ static struct { { PCI_DID_INTEL_RPL_HX_ID_6, "Raptorlake-HX (8+8)" }, { PCI_DID_INTEL_RPL_HX_ID_7, "Raptorlake-HX (6+8)" }, { PCI_DID_INTEL_RPL_HX_ID_8, "Raptorlake-HX (6+4)" }, - { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-P" }, - { PCI_DID_INTEL_RPL_P_ID_5, "Raptorlake-P" }, + { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P/H/H Refresh (6+8)" }, + { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P/H/H Refresh (4+8)" }, + { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-U/U Refresh (2+8)" }, + { PCI_DID_INTEL_RPL_P_ID_4, "Raptorlake-U/U Refresh (2+4)" }, + { PCI_DID_INTEL_RPL_P_ID_5, "Raptorlake-U (1+4)" }, + { PCI_DID_INTEL_RPL_P_ID_6, "Raptorlake-PX (6+8)" }, + { PCI_DID_INTEL_RPL_P_ID_7, "Raptorlake-PX (4+8)" }, + { PCI_DID_INTEL_RPL_P_ID_8, "Raptorlake-H (4+4)" }, { PCI_DID_INTEL_RPL_S_ID_1, "Raptorlake-S (8+16)" }, { PCI_DID_INTEL_RPL_S_ID_2, "Raptorlake-S (8+0)" }, { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (8+8)" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 437d675ecf..1620c10b6e 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -176,6 +176,9 @@ static const struct { { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W }, + { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W }, { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 2d25bb653a..5b1a690b9e 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -268,6 +268,9 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_RPL_P_ID_3, PCI_DID_INTEL_RPL_P_ID_4, PCI_DID_INTEL_RPL_P_ID_5, + PCI_DID_INTEL_RPL_P_ID_6, + PCI_DID_INTEL_RPL_P_ID_7, + PCI_DID_INTEL_RPL_P_ID_8, }; const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT), diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 5720c86472..4ddf1e42d6 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -528,6 +528,9 @@ static uint16_t get_vccin_aux_imon_iccmax(void) case PCI_DID_INTEL_RPL_P_ID_3: case PCI_DID_INTEL_RPL_P_ID_4: case PCI_DID_INTEL_RPL_P_ID_5: + case PCI_DID_INTEL_RPL_P_ID_6: + case PCI_DID_INTEL_RPL_P_ID_7: + case PCI_DID_INTEL_RPL_P_ID_8: tdp = get_cpu_tdp(); if (tdp == TDP_45W) return ICC_MAX_TDP_45W; diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 6718e89a44..c3584ba01f 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -134,6 +134,9 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, @@ -195,6 +198,9 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, @@ -256,6 +262,9 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -317,6 +326,9 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, { PCI_DID_INTEL_RPL_P_ID_5, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(22, 22) }, + { PCI_DID_INTEL_RPL_P_ID_6, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, + { PCI_DID_INTEL_RPL_P_ID_7, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, + { PCI_DID_INTEL_RPL_P_ID_8, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 22) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 99c145d56a..b53814e35d 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -535,6 +535,9 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_RPL_P_ID_3, PCI_DID_INTEL_RPL_P_ID_4, PCI_DID_INTEL_RPL_P_ID_5, + PCI_DID_INTEL_RPL_P_ID_6, + PCI_DID_INTEL_RPL_P_ID_7, + PCI_DID_INTEL_RPL_P_ID_8, 0 }; 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