From c8b7215639bcb5f3812bc33fe93b537ede15bad0 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Jul 2020 12:30:54 +0300 Subject: mb/intel/cedarisland: Use FSP_M_CONFIG structure to set UPD According to src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h, use FSP_M_CONFIG structure fields to configure UPD options for FSP-M in romstage instead of raw offsets. Change-Id: Idb25d8954b09805b496ab97b341a8ef1ac38bb6a Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/43923 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/cedarisland_crb/romstage.c | 21 +++++---------------- 1 file changed, 5 insertions(+), 16 deletions(-) (limited to 'src') diff --git a/src/mainboard/intel/cedarisland_crb/romstage.c b/src/mainboard/intel/cedarisland_crb/romstage.c index e82d26b1e1..8468605484 100644 --- a/src/mainboard/intel/cedarisland_crb/romstage.c +++ b/src/mainboard/intel/cedarisland_crb/romstage.c @@ -1,25 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include void mainboard_memory_init_params(FSPM_UPD *mupd) { FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - void *start = (void *) m_cfg; - // BoardId - write8(start + 140, 0x1d); - - // BoardTypeBitmask - write32(start + 104, 0x11111111); - - // DebugPrintLevel - write8(start + 45, 8); - - // KtiLinkSpeedMode - write8(start + 64, 0); - - // KtiPrefetchEn - write8(start + 53, 2); + m_cfg->BoardId = 0x1d; + m_cfg->BoardTypeBitmask = 0x11111111; + m_cfg->DebugPrintLevel = 8; + m_cfg->KtiLinkSpeedMode = 0; + m_cfg->KtiPrefetchEn = 2; } -- cgit v1.2.3