From c6f27226a84434182771dbbcd593d223072801f7 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Wed, 3 Apr 2013 09:56:57 -0500 Subject: sandybridge: enable ROM caching If ROM caching is selected the sandybridge chipset code will will enable ROM caching after all other CPU threads are brought up. Change-Id: I3a57ba8753678146527ebf9547f5fbbd4f441f43 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/3017 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/northbridge/intel/sandybridge/northbridge.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index c39933f1c1..b8022b8cea 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include #include @@ -486,6 +487,8 @@ static const struct pci_driver mc_driver_1 __pci_driver = { static void cpu_bus_init(device_t dev) { initialize_cpus(dev->link_list); + /* Enable ROM caching if option was selected. */ + x86_mtrr_enable_rom_caching(); } static void cpu_bus_noop(device_t dev) -- cgit v1.2.3