From c6e26fbf852c98730d836a620bad522a7470ce50 Mon Sep 17 00:00:00 2001 From: Raihow Shi Date: Fri, 19 Aug 2022 19:16:35 +0800 Subject: mb/google/brask/variants/moli: Override tdp pl1 value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w. BUG=b:236294162 TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct. Signed-off-by: Raihow Shi Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910 Reviewed-by: Tim Wawrzynczak Reviewed-by: Sumeet R Pawnikar Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/moli/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/moli/overridetree.cb b/src/mainboard/google/brya/variants/moli/overridetree.cb index e5a9a0439f..ab984e158b 100644 --- a/src/mainboard/google/brya/variants/moli/overridetree.cb +++ b/src/mainboard/google/brya/variants/moli/overridetree.cb @@ -34,6 +34,12 @@ chip soc/intel/alderlake }" # Type-A port A2 register "tcss_ports[3]" = "TCSS_PORT_EMPTY" # Disable TCP3 register "tcc_offset" = "0" # TCC of 100C + register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ + .tdp_pl1_override = 55, + }" + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + .tdp_pl1_override = 64, + }" device domain 0 on device ref dtt on chip drivers/intel/dptf -- cgit v1.2.3