From c64a6d63ed9cbd20d8acd8d50ce76af275cca526 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 23 Sep 2016 15:06:37 -0500 Subject: soc/intel/apollolake: provide power button ACPI device Instead of having each mainboard provide the power button, uncondtionally provide the power button ACPI device on behalf of each mainboard. BUG=chrome-os-partner:56677 Change-Id: I94c9e0353c8d829136f0d52a356286c6bedcddd5 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/16731 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie --- src/mainboard/google/reef/dsdt.asl | 7 +------ src/soc/intel/apollolake/acpi/southbridge.asl | 9 +++++++++ 2 files changed, 10 insertions(+), 6 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 3265941071..bfdd765699 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include - /* LID and Power button. */ + /* LID */ Scope (\_SB) { Device (LID0) @@ -58,11 +58,6 @@ DefinitionBlock( } Name (_PRW, Package () { GPE_EC_WAKE, 0x3 }) } - - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } } /* Chrome OS Embedded Controller */ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f924..1c10f1a5ed 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,15 @@ #include +/* Power button. */ +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + /* PCIE device */ #include "pcie.asl" -- cgit v1.2.3