From c583920a748fb8bd7999142433ad08641b06283d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 23:48:42 +0100 Subject: nb/intel/i945: Initialize console in bootblock Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/ec/lenovo/pmh7/Makefile.inc | 1 + src/mainboard/apple/macbook21/Makefile.inc | 2 + src/mainboard/apple/macbook21/early_init.c | 50 +++++++ src/mainboard/apple/macbook21/romstage.c | 50 ------- src/mainboard/asus/p5gc-mx/Makefile.inc | 2 + src/mainboard/asus/p5gc-mx/early_init.c | 118 ++++++++++++++++ src/mainboard/asus/p5gc-mx/romstage.c | 117 ---------------- src/mainboard/getac/p470/Makefile.inc | 2 + src/mainboard/getac/p470/early_init.c | 155 +++++++++++++++++++++ src/mainboard/getac/p470/romstage.c | 154 -------------------- src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc | 2 + src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c | 61 ++++++++ src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 60 -------- src/mainboard/ibase/mb899/Makefile.inc | 2 + src/mainboard/ibase/mb899/early_init.c | 119 ++++++++++++++++ src/mainboard/ibase/mb899/romstage.c | 118 ---------------- src/mainboard/intel/d945gclf/Makefile.inc | 2 + src/mainboard/intel/d945gclf/early_init.c | 48 +++++++ src/mainboard/intel/d945gclf/romstage.c | 47 ------- src/mainboard/kontron/986lcd-m/Makefile.inc | 2 + src/mainboard/kontron/986lcd-m/early_init.c | 162 ++++++++++++++++++++++ src/mainboard/kontron/986lcd-m/romstage.c | 161 --------------------- src/mainboard/lenovo/t60/Makefile.inc | 4 + src/mainboard/lenovo/t60/early_init.c | 105 ++++++++++++++ src/mainboard/lenovo/t60/romstage.c | 104 -------------- src/mainboard/lenovo/x60/Makefile.inc | 4 + src/mainboard/lenovo/x60/early_init.c | 105 ++++++++++++++ src/mainboard/lenovo/x60/romstage.c | 104 -------------- src/mainboard/roda/rk886ex/Makefile.inc | 2 + src/mainboard/roda/rk886ex/early_init.c | 131 +++++++++++++++++ src/mainboard/roda/rk886ex/romstage.c | 130 ----------------- src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/i945/i945.h | 2 - src/northbridge/intel/i945/romstage.c | 9 -- src/southbridge/intel/common/Makefile.inc | 1 + 35 files changed, 1080 insertions(+), 1057 deletions(-) create mode 100644 src/mainboard/apple/macbook21/early_init.c delete mode 100644 src/mainboard/apple/macbook21/romstage.c create mode 100644 src/mainboard/asus/p5gc-mx/early_init.c delete mode 100644 src/mainboard/asus/p5gc-mx/romstage.c create mode 100644 src/mainboard/getac/p470/early_init.c delete mode 100644 src/mainboard/getac/p470/romstage.c create mode 100644 src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c delete mode 100644 src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c create mode 100644 src/mainboard/ibase/mb899/early_init.c delete mode 100644 src/mainboard/ibase/mb899/romstage.c create mode 100644 src/mainboard/intel/d945gclf/early_init.c delete mode 100644 src/mainboard/intel/d945gclf/romstage.c create mode 100644 src/mainboard/kontron/986lcd-m/early_init.c delete mode 100644 src/mainboard/kontron/986lcd-m/romstage.c create mode 100644 src/mainboard/lenovo/t60/early_init.c delete mode 100644 src/mainboard/lenovo/t60/romstage.c create mode 100644 src/mainboard/lenovo/x60/early_init.c delete mode 100644 src/mainboard/lenovo/x60/romstage.c create mode 100644 src/mainboard/roda/rk886ex/early_init.c delete mode 100644 src/mainboard/roda/rk886ex/romstage.c (limited to 'src') diff --git a/src/ec/lenovo/pmh7/Makefile.inc b/src/ec/lenovo/pmh7/Makefile.inc index d5524dca1f..c7c95c0009 100644 --- a/src/ec/lenovo/pmh7/Makefile.inc +++ b/src/ec/lenovo/pmh7/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_EC_LENOVO_PMH7),y) +bootblock-y += pmh7.c ramstage-y += pmh7.c smm-y += pmh7.c romstage-y += pmh7.c diff --git a/src/mainboard/apple/macbook21/Makefile.inc b/src/mainboard/apple/macbook21/Makefile.inc index 3dae61e8a8..b4f8b6573a 100644 --- a/src/mainboard/apple/macbook21/Makefile.inc +++ b/src/mainboard/apple/macbook21/Makefile.inc @@ -1 +1,3 @@ romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/apple/macbook21/early_init.c b/src/mainboard/apple/macbook21/early_init.c new file mode 100644 index 0000000000..d4654de118 --- /dev/null +++ b/src/mainboard/apple/macbook21/early_init.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +void mainboard_late_rcba_config(void) +{ + /* V0CTL Virtual Channel 0 Resource Control */ + RCBA32(0x0014) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(0x3100) = 0x00042210; + RCBA32(0x3108) = 0x10004321; + + /* PCIe Interrupts */ + RCBA32(D28IP) = 0x00214321; + /* HD Audio Interrupt */ + RCBA32(D27IP) = 0x00000001; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0232; + RCBA16(D30IR) = 0x3246; + RCBA16(D29IR) = 0x0235; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x3216; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c deleted file mode 100644 index d4654de118..0000000000 --- a/src/mainboard/apple/macbook21/romstage.c +++ /dev/null @@ -1,50 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include - -void mainboard_late_rcba_config(void) -{ - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(0x3100) = 0x00042210; - RCBA32(0x3108) = 0x10004321; - - /* PCIe Interrupts */ - RCBA32(D28IP) = 0x00214321; - /* HD Audio Interrupt */ - RCBA32(D27IP) = 0x00000001; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0232; - RCBA16(D30IR) = 0x3246; - RCBA16(D29IR) = 0x0235; - RCBA16(D28IR) = 0x3201; - RCBA16(D27IR) = 0x3216; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; -} diff --git a/src/mainboard/asus/p5gc-mx/Makefile.inc b/src/mainboard/asus/p5gc-mx/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/asus/p5gc-mx/Makefile.inc +++ b/src/mainboard/asus/p5gc-mx/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asus/p5gc-mx/early_init.c b/src/mainboard/asus/p5gc-mx/early_init.c new file mode 100644 index 0000000000..6d37fed2ef --- /dev/null +++ b/src/mainboard/asus/p5gc-mx/early_init.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) + +/* + * BSEL0 is connected with GPIO32 + * BSEL1 is connected with GPIO33 with inversed logic + * BSEL2 is connected with GPIO55 + */ +static int setup_sio_gpio(u8 bsel) +{ + int need_reset = 0; + u8 reg, old_reg; + + pnp_enter_ext_func_mode(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + + reg = 0x9a; + old_reg = pnp_read_config(GPIO_DEV, 0x2c); + pnp_write_config(GPIO_DEV, 0x2c, reg); + need_reset = (reg != old_reg); + + pnp_write_config(GPIO_DEV, 0x30, 0x0e); + pnp_write_config(GPIO_DEV, 0xe0, 0xde); + pnp_write_config(GPIO_DEV, 0xf0, 0xf3); + pnp_write_config(GPIO_DEV, 0xf4, 0x80); + pnp_write_config(GPIO_DEV, 0xf5, 0x80); + + /* Invert GPIO33 */ + pnp_write_config(GPIO_DEV, 0xf2, 0x08); + + reg = (bsel & 3) << 2; + old_reg = pnp_read_config(GPIO_DEV, 0xf1); + pnp_write_config(GPIO_DEV, 0xf1, reg); + need_reset += ((reg & 0xc) != (old_reg & 0xc)); + + reg = (bsel >> 2) << 5; + old_reg = pnp_read_config(GPIO_DEV, 0xe1); + pnp_write_config(GPIO_DEV, 0xe1, reg); + need_reset += ((reg & 0x20) != (old_reg & 0x20)); + + pnp_exit_ext_func_mode(GPIO_DEV); + + return need_reset; +} + +static u8 msr_get_fsb(void) +{ + u8 fsbcfg; + msr_t msr; + const u32 eax = cpuid_eax(1); + + /* Netburst */ + if (((eax >> 8) & 0xf) == 0xf) { + msr = rdmsr(MSR_EBC_FREQUENCY_ID); + fsbcfg = (msr.lo >> 16) & 0x7; + } else { /* Intel Core 2 */ + msr = rdmsr(MSR_FSB_FREQ); + fsbcfg = msr.lo & 0x7; + } + + return fsbcfg; +} + +void mainboard_late_rcba_config(void) +{ + /* Enable PCIe Root Port Clock Gate */ + RCBA32(CG) = 0x00000001; +} + +void mainboard_pre_raminit_config(int s3_resume) +{ + u8 c_bsel = msr_get_fsb(); + /* + * Result is that FSB is incorrect on s3 resume (fixed at 800MHz). + * Some CPU accept this others don't. + */ + if (!s3_resume && setup_sio_gpio(c_bsel)) { + printk(BIOS_DEBUG, + "Needs reset to configure CPU BSEL straps\n"); + full_reset(); + } +} + +void bootblock_mainboard_early_init(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c deleted file mode 100644 index eef603bbf5..0000000000 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz - * Copyright (C) 2016 Kyösti Mälkki - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) - -/* - * BSEL0 is connected with GPIO32 - * BSEL1 is connected with GPIO33 with inversed logic - * BSEL2 is connected with GPIO55 - */ -static int setup_sio_gpio(u8 bsel) -{ - int need_reset = 0; - u8 reg, old_reg; - - pnp_enter_ext_func_mode(GPIO_DEV); - pnp_set_logical_device(GPIO_DEV); - - reg = 0x9a; - old_reg = pnp_read_config(GPIO_DEV, 0x2c); - pnp_write_config(GPIO_DEV, 0x2c, reg); - need_reset = (reg != old_reg); - - pnp_write_config(GPIO_DEV, 0x30, 0x0e); - pnp_write_config(GPIO_DEV, 0xe0, 0xde); - pnp_write_config(GPIO_DEV, 0xf0, 0xf3); - pnp_write_config(GPIO_DEV, 0xf4, 0x80); - pnp_write_config(GPIO_DEV, 0xf5, 0x80); - - /* Invert GPIO33 */ - pnp_write_config(GPIO_DEV, 0xf2, 0x08); - - reg = (bsel & 3) << 2; - old_reg = pnp_read_config(GPIO_DEV, 0xf1); - pnp_write_config(GPIO_DEV, 0xf1, reg); - need_reset += ((reg & 0xc) != (old_reg & 0xc)); - - reg = (bsel >> 2) << 5; - old_reg = pnp_read_config(GPIO_DEV, 0xe1); - pnp_write_config(GPIO_DEV, 0xe1, reg); - need_reset += ((reg & 0x20) != (old_reg & 0x20)); - - pnp_exit_ext_func_mode(GPIO_DEV); - - return need_reset; -} - -static u8 msr_get_fsb(void) -{ - u8 fsbcfg; - msr_t msr; - const u32 eax = cpuid_eax(1); - - /* Netburst */ - if (((eax >> 8) & 0xf) == 0xf) { - msr = rdmsr(MSR_EBC_FREQUENCY_ID); - fsbcfg = (msr.lo >> 16) & 0x7; - } else { /* Intel Core 2 */ - msr = rdmsr(MSR_FSB_FREQ); - fsbcfg = msr.lo & 0x7; - } - - return fsbcfg; -} - -void mainboard_late_rcba_config(void) -{ - /* Enable PCIe Root Port Clock Gate */ - RCBA32(CG) = 0x00000001; -} - -void mainboard_pre_raminit_config(int s3_resume) -{ - u8 c_bsel = msr_get_fsb(); - /* - * Result is that FSB is incorrect on s3 resume (fixed at 800MHz). - * Some CPU accept this others don't. - */ - if (!s3_resume && setup_sio_gpio(c_bsel)) { - printk(BIOS_DEBUG, - "Needs reset to configure CPU BSEL straps\n"); - full_reset(); - } -} - -void mainboard_superio_config(void) -{ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} diff --git a/src/mainboard/getac/p470/Makefile.inc b/src/mainboard/getac/p470/Makefile.inc index ed9d39cec6..c8c8e0cc4a 100644 --- a/src/mainboard/getac/p470/Makefile.inc +++ b/src/mainboard/getac/p470/Makefile.inc @@ -15,3 +15,5 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c new file mode 100644 index 0000000000..3684c1c943 --- /dev/null +++ b/src/mainboard/getac/p470/early_init.c @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "option_table.h" + +void mainboard_pre_raminit_config(int s3_resume) +{ + u32 gpios; + + printk(BIOS_SPEW, "\n Initializing drive bay...\n"); + gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 + gpios |= (1 << 0); // GPIO33 = ODD + gpios |= (1 << 1); // GPIO34 = IDE_RST# + outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ + + gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level + gpios &= ~(1 << 13); // ?? + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + + printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); + gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level + gpios &= ~(1 << 24); // Enable LAN Power + outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ +} + +/* Override the default lpc decode ranges */ +void mainboard_lpc_decode(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) + lpt_en = LPT_LPC_EN; + + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); + // decode range + pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); +} + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +void bootblock_mainboard_early_init(void) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(0x4e, 0x00); + + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, 0x02, 0x0e); // UART power + pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base + pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base + pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ + pnp_write_config(dev, 0x1e, 1); // no 32khz clock + pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base + pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ + pnp_write_config(dev, 0x2c, 0); // DMA0 FIR + pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base + + pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR + pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL + pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR + pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL + pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR + pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL + pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR + pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL + + pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT + pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT + pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT + pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR + pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL + pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 + pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 + pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 + + pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 + pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 + pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 + pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 + pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 + pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 + + pnp_exit_ext_func_mode(dev); +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00042220; + /* Device 1d interrupt pin register */ + RCBA32(D28IP) = 0x00214321; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0232; + RCBA16(D30IR) = 0x3246; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x3216; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; + + /* This should probably go into the ACPI enable trap */ + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA32(0x1e84) = 0x00020001; + RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c deleted file mode 100644 index 2da9d06ff9..0000000000 --- a/src/mainboard/getac/p470/romstage.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "option_table.h" - -void mainboard_pre_raminit_config(int s3_resume) -{ - u32 gpios; - - printk(BIOS_SPEW, "\n Initializing drive bay...\n"); - gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2 - gpios |= (1 << 0); // GPIO33 = ODD - gpios |= (1 << 1); // GPIO34 = IDE_RST# - outl(gpios, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */ - - gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level - gpios &= ~(1 << 13); // ?? - outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ - - printk(BIOS_SPEW, "\n Initializing Ethernet NIC...\n"); - gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level - gpios &= ~(1 << 24); // Enable LAN Power - outl(gpios, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ -} - -/* Override the default lpc decode ranges */ -void mainboard_lpc_decode(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) - lpt_en = LPT_LPC_EN; - - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); - // decode range - pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); -} - -/* This box has two superios, so enabling serial becomes slightly excessive. - * We disable a lot of stuff to make sure that there are no conflicts between - * the two. Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -static void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0xaa, port); -} - -void mainboard_superio_config(void) -{ - pnp_devfn_t dev; - - dev = PNP_DEV(0x4e, 0x00); - - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, 0x02, 0x0e); // UART power - pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base - pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base - pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ - pnp_write_config(dev, 0x1e, 1); // no 32khz clock - pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base - pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ - pnp_write_config(dev, 0x2c, 0); // DMA0 FIR - pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base - - pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR - pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL - pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR - pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL - pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR - pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL - pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR - pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL - - pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT - pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT - pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT - pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR - pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL - pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1 - pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2 - pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3 - - pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5 - pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6 - pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7 - pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8 - pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9 - pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10 - - pnp_exit_ext_func_mode(dev); -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00042220; - /* Device 1d interrupt pin register */ - RCBA32(D28IP) = 0x00214321; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0232; - RCBA16(D30IR) = 0x3246; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3201; - RCBA16(D27IR) = 0x3216; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; - - /* This should probably go into the ACPI enable trap */ - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(0x1e84) = 0x00020001; - RCBA32(0x1e80) = 0x0000fe01; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; -} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c new file mode 100644 index 0000000000..7b82059580 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x40); + ite_reg_write(GPIO_DEV, 0x26, 0x3f); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x88); + ite_reg_write(GPIO_DEV, 0x2c, 0x1c); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_kill_watchdog(GPIO_DEV); + ite_reg_write(GPIO_DEV, 0xb1, 0x01); + ite_reg_write(GPIO_DEV, 0xb8, 0x80); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc3, 0x00); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x01); + + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0xff); // Enable + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); +} + +void mainboard_late_rcba_config(void) +{ + /* Enable PCIe Root Port Clock Gate */ + RCBA32(CG) = 0x00000001; +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c deleted file mode 100644 index 467a66f959..0000000000 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -void mainboard_superio_config(void) -{ - /* Set default GPIOs on superio */ - ite_reg_write(GPIO_DEV, 0x25, 0x40); - ite_reg_write(GPIO_DEV, 0x26, 0x3f); - ite_reg_write(GPIO_DEV, 0x28, 0x41); - ite_reg_write(GPIO_DEV, 0x29, 0x88); - ite_reg_write(GPIO_DEV, 0x2c, 0x1c); - ite_reg_write(GPIO_DEV, 0x62, 0x08); - ite_kill_watchdog(GPIO_DEV); - ite_reg_write(GPIO_DEV, 0xb1, 0x01); - ite_reg_write(GPIO_DEV, 0xb8, 0x80); - ite_reg_write(GPIO_DEV, 0xbb, 0x40); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc3, 0x00); - ite_reg_write(GPIO_DEV, 0xc8, 0x00); - ite_reg_write(GPIO_DEV, 0xcb, 0x00); - ite_reg_write(GPIO_DEV, 0xf6, 0x26); - ite_reg_write(GPIO_DEV, 0xfc, 0x01); - - ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 - ite_reg_write(EC_DEV, 0x30, 0xff); // Enable - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); -} - -void mainboard_late_rcba_config(void) -{ - /* Enable PCIe Root Port Clock Gate */ - RCBA32(CG) = 0x00000001; -} diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc index 3f072f553f..992c3736a7 100644 --- a/src/mainboard/ibase/mb899/Makefile.inc +++ b/src/mainboard/ibase/mb899/Makefile.inc @@ -1,3 +1,5 @@ ramstage-y += superio_hwm.c ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c new file mode 100644 index 0000000000..ba8d30cf29 --- /dev/null +++ b/src/mainboard/ibase/mb899/early_init.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +/* This box has one superio + * Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +void bootblock_mainboard_early_init(void) +{ + pnp_devfn_t dev; + + dev = SUPERIO_DEV; + pnp_enter_conf_state(dev); + + pnp_write_config(dev, 0x24, 0xc4); // PNPCVS + + pnp_write_config(dev, 0x29, 0x01); // GPIO settings + pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 + pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? + pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? + pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? + + dev = PNP_DEV(0x4e, W83627EHG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627EHG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + //pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627EHG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); // Just enable it + + dev = PNP_DEV(0x4e, W83627EHG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + + dev = PNP_DEV(0x4e, W83627EHG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, W83627EHG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + /* Enable HWM */ + dev = PNP_DEV(0x4e, W83627EHG_HWM); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(D28IP) = 0x00214321; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x0146; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x0146; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c deleted file mode 100644 index 2bc3cde103..0000000000 --- a/src/mainboard/ibase/mb899/romstage.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) - -/* This box has one superio - * Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -void mainboard_superio_config(void) -{ - pnp_devfn_t dev; - - dev = SUPERIO_DEV; - pnp_enter_conf_state(dev); - - pnp_write_config(dev, 0x24, 0xc4); // PNPCVS - - pnp_write_config(dev, 0x29, 0x01); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 - pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? - pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? - pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? - - dev = PNP_DEV(0x4e, W83627EHG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627EHG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627EHG_GPIO2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it - - dev = PNP_DEV(0x4e, W83627EHG_GPIO3); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient - - dev = PNP_DEV(0x4e, W83627EHG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x4e, W83627EHG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - /* Enable HWM */ - dev = PNP_DEV(0x4e, W83627EHG_HWM); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(D28IP) = 0x00214321; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x0146; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3201; - RCBA16(D27IR) = 0x0146; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; -} diff --git a/src/mainboard/intel/d945gclf/Makefile.inc b/src/mainboard/intel/d945gclf/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/intel/d945gclf/Makefile.inc +++ b/src/mainboard/intel/d945gclf/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/intel/d945gclf/early_init.c b/src/mainboard/intel/d945gclf/early_init.c new file mode 100644 index 0000000000..c8dd3619c8 --- /dev/null +++ b/src/mainboard/intel/d945gclf/early_init.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) +#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x0146; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x0146; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} + +void bootblock_mainboard_early_init(void) +{ + /* Enable SuperIO PM */ + lpc47m15x_enable_serial(PME_DEV, 0x680); + lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ +} diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c deleted file mode 100644 index 7a8f5d1656..0000000000 --- a/src/mainboard/intel/d945gclf/romstage.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) -#define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x0146; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3201; - RCBA16(D27IR) = 0x0146; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; -} - -void mainboard_superio_config(void) -{ - /* Enable SuperIO PM */ - lpc47m15x_enable_serial(PME_DEV, 0x680); - lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */ -} diff --git a/src/mainboard/kontron/986lcd-m/Makefile.inc b/src/mainboard/kontron/986lcd-m/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/kontron/986lcd-m/Makefile.inc +++ b/src/mainboard/kontron/986lcd-m/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/kontron/986lcd-m/early_init.c b/src/mainboard/kontron/986lcd-m/early_init.c new file mode 100644 index 0000000000..48fe4935ae --- /dev/null +++ b/src/mainboard/kontron/986lcd-m/early_init.c @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "option_table.h" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) + +/* Override the default lpc decode ranges */ +void mainboard_lpc_decode(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) + lpt_en = LPT_LPC_EN; /* enable LPT */ + + pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); +} + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +void bootblock_mainboard_early_init(void) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(0x2e, W83627THG_SP1); + pnp_enter_conf_state(dev); + + pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ + + pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ + pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ + + dev = PNP_DEV(0x2e, W83627THG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x2e, W83627THG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x2e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x2e, W83627THG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); /* Just enable it */ + + dev = PNP_DEV(0x2e, W83627THG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ + pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ + pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ + + dev = PNP_DEV(0x2e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x2e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + /* Enable HWM */ + dev = PNP_DEV(0x2e, W83627THG_HWM); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); + + dev = PNP_DEV(0x4e, W83627THG_SP1); + pnp_enter_conf_state(dev); + + pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 11); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627THG_SP2); + pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 10); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627THG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, W83627THG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, W83627THG_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); + + pnp_exit_conf_state(dev); +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(D28IP) = 0x00214321; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x3241; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3210; + RCBA16(D27IR) = 0x3210; + + /* Enable PCIe Root Port Clock Gate */ +} diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c deleted file mode 100644 index 2c894534f3..0000000000 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ /dev/null @@ -1,161 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#include "option_table.h" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) - -/* Override the default lpc decode ranges */ -void mainboard_lpc_decode(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) - lpt_en = LPT_LPC_EN; /* enable LPT */ - - pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); -} - -/* This box has two superios, so enabling serial becomes slightly excessive. - * We disable a lot of stuff to make sure that there are no conflicts between - * the two. Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -void mainboard_superio_config(void) -{ - pnp_devfn_t dev; - - dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_enter_conf_state(dev); - - pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ - - pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ - pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ - - dev = PNP_DEV(0x2e, W83627THG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x2e, W83627THG_GPIO2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); /* Just enable it */ - - dev = PNP_DEV(0x2e, W83627THG_GPIO3); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ - pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ - pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ - - dev = PNP_DEV(0x2e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x2e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - /* Enable HWM */ - dev = PNP_DEV(0x2e, W83627THG_HWM); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); - - dev = PNP_DEV(0x4e, W83627THG_SP1); - pnp_enter_conf_state(dev); - - pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 11); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627THG_SP2); - pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 10); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627THG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x4e, W83627THG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x4e, W83627THG_KBC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); - - pnp_exit_conf_state(dev); -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(D28IP) = 0x00214321; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x3241; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3210; - RCBA16(D27IR) = 0x3210; - - /* Enable PCIe Root Port Clock Gate */ -} diff --git a/src/mainboard/lenovo/t60/Makefile.inc b/src/mainboard/lenovo/t60/Makefile.inc index f646af8fd5..b604b6b126 100644 --- a/src/mainboard/lenovo/t60/Makefile.inc +++ b/src/mainboard/lenovo/t60/Makefile.inc @@ -14,5 +14,9 @@ ## smm-y += dock.c +bootblock-y += dock.c romstage-y += dock.c +bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/t60/early_init.c b/src/mainboard/lenovo/t60/early_init.c new file mode 100644 index 0000000000..d3de1e4c94 --- /dev/null +++ b/src/mainboard/lenovo/t60/early_init.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dock.h" + +/* Override the default lpc decode ranges */ +void mainboard_lpc_decode(void) +{ + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); +} + +static void early_superio_config(void) +{ + int timeout = 100000; + pnp_devfn_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0xa0); + + while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); + setup_pch_gpios(&mainboard_gpio_map); + + int dock_err = dlpc_init(); + + /* We prefer Legacy I/O module over docking */ + if (legacy_io_present()) { + legacy_io_init(); + early_superio_config(); + } else if (!dock_err && dock_present()) { + dock_connect(); + early_superio_config(); + } +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(V0CTL) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00001230; + RCBA32(D29IP) = 0x40004321; + + /* PCIe Interrupts */ + RCBA32(D28IP) = 0x00004321; + /* HD Audio Interrupt */ + RCBA32(D27IP) = 0x00000002; + + /* dev irq route register */ + RCBA16(D31IR) = 0x1007; + RCBA16(D30IR) = 0x0076; + RCBA16(D29IR) = 0x3210; + RCBA16(D28IR) = 0x7654; + RCBA16(D27IR) = 0x0010; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA64(IOTR0) = 0x000200010000fe01ULL; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA64(IOTR3) = 0x000200f0000c0801ULL; +} + +void mainboard_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x51; +} diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c deleted file mode 100644 index 5076ada75f..0000000000 --- a/src/mainboard/lenovo/t60/romstage.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "dock.h" - -/* Override the default lpc decode ranges */ -void mainboard_lpc_decode(void) -{ - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - pnp_devfn_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0xa0); - - while(!(pnp_read_config(dev, 0x29) & 0x10) && timeout--) - udelay(1000); - - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); -} - -void mainboard_superio_config(void) -{ - /* Set up GPIO's early since it is needed for dock init */ - i82801gx_setup_bars(); - setup_pch_gpios(&mainboard_gpio_map); - - int dock_err = dlpc_init(); - - /* We prefer Legacy I/O module over docking */ - if (legacy_io_present()) { - legacy_io_init(); - early_superio_config(); - } else if (!dock_err && dock_present()) { - dock_connect(); - early_superio_config(); - } -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00001230; - RCBA32(D29IP) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(D28IP) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(D27IP) = 0x00000002; - - /* dev irq route register */ - RCBA16(D31IR) = 0x1007; - RCBA16(D30IR) = 0x0076; - RCBA16(D29IR) = 0x3210; - RCBA16(D28IR) = 0x7654; - RCBA16(D27IR) = 0x0010; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA64(IOTR0) = 0x000200010000fe01ULL; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA64(IOTR3) = 0x000200f0000c0801ULL; -} - -void mainboard_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x51; -} diff --git a/src/mainboard/lenovo/x60/Makefile.inc b/src/mainboard/lenovo/x60/Makefile.inc index a7ad539a1f..7fb2f0268e 100644 --- a/src/mainboard/lenovo/x60/Makefile.inc +++ b/src/mainboard/lenovo/x60/Makefile.inc @@ -14,6 +14,10 @@ ## smm-y += dock.c +bootblock-y += dock.c romstage-y += dock.c ramstage-y += dock.c +bootblock-y += gpio.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/lenovo/x60/early_init.c b/src/mainboard/lenovo/x60/early_init.c new file mode 100644 index 0000000000..459c2461ca --- /dev/null +++ b/src/mainboard/lenovo/x60/early_init.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "dock.h" + +/* Override the default lpc decode ranges */ +void mainboard_lpc_decode(void) +{ + // decode range + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); +} + +static void early_superio_config(void) +{ + int timeout = 100000; + pnp_devfn_t dev = PNP_DEV(0x2e, 3); + + pnp_write_config(dev, 0x29, 0x06); + + while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) + udelay(1000); + + /* Enable COM1 */ + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_enable(dev, 1); +} + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIO's early since it is needed for dock init */ + i82801gx_setup_bars(); + setup_pch_gpios(&mainboard_gpio_map); + + dlpc_init(); + /* dock_init initializes the DLPC switch on + * thinpad side, so this is required even + * if we're undocked. + */ + if (dock_present()) { + dock_connect(); + early_superio_config(); + } +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + RCBA32(V0CTL) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00001230; + RCBA32(D29IP) = 0x40004321; + + /* PCIe Interrupts */ + RCBA32(D28IP) = 0x00004321; + /* HD Audio Interrupt */ + RCBA32(D27IP) = 0x00000002; + + /* dev irq route register */ + RCBA16(D31IR) = 0x1007; + RCBA16(D30IR) = 0x0076; + RCBA16(D29IR) = 0x3210; + RCBA16(D28IR) = 0x7654; + RCBA16(D27IR) = 0x0010; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA64(IOTR0) = 0x000200010000fe01ULL; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA64(IOTR3) = 0x000200f0000c0801ULL; +} + + +void mainboard_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x51; +} diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c deleted file mode 100644 index d230aa3c57..0000000000 --- a/src/mainboard/lenovo/x60/romstage.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011 Sven Schnelle - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include "dock.h" - -/* Override the default lpc decode ranges */ -void mainboard_lpc_decode(void) -{ - // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); -} - -static void early_superio_config(void) -{ - int timeout = 100000; - pnp_devfn_t dev = PNP_DEV(0x2e, 3); - - pnp_write_config(dev, 0x29, 0x06); - - while (!(pnp_read_config(dev, 0x29) & 0x08) && timeout--) - udelay(1000); - - /* Enable COM1 */ - pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_enable(dev, 1); -} - -void mainboard_superio_config(void) -{ - /* Set up GPIO's early since it is needed for dock init */ - i82801gx_setup_bars(); - setup_pch_gpios(&mainboard_gpio_map); - - dlpc_init(); - /* dock_init initializes the DLPC switch on - * thinpad side, so this is required even - * if we're undocked. - */ - if (dock_present()) { - dock_connect(); - early_superio_config(); - } -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00001230; - RCBA32(D29IP) = 0x40004321; - - /* PCIe Interrupts */ - RCBA32(D28IP) = 0x00004321; - /* HD Audio Interrupt */ - RCBA32(D27IP) = 0x00000002; - - /* dev irq route register */ - RCBA16(D31IR) = 0x1007; - RCBA16(D30IR) = 0x0076; - RCBA16(D29IR) = 0x3210; - RCBA16(D28IR) = 0x7654; - RCBA16(D27IR) = 0x0010; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA64(IOTR0) = 0x000200010000fe01ULL; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA64(IOTR3) = 0x000200f0000c0801ULL; -} - - -void mainboard_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - spd_map[2] = 0x51; -} diff --git a/src/mainboard/roda/rk886ex/Makefile.inc b/src/mainboard/roda/rk886ex/Makefile.inc index 2c68d384d1..ab011673fd 100644 --- a/src/mainboard/roda/rk886ex/Makefile.inc +++ b/src/mainboard/roda/rk886ex/Makefile.inc @@ -16,3 +16,5 @@ ramstage-y += m3885.c ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/roda/rk886ex/early_init.c b/src/mainboard/roda/rk886ex/early_init.c new file mode 100644 index 0000000000..dff1a6fe03 --- /dev/null +++ b/src/mainboard/roda/rk886ex/early_init.c @@ -0,0 +1,131 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "option_table.h" + +/* Override the default lpc decode ranges */ +void mainboard_lpc_decode(void) +{ + int lpt_en = 0; + if (read_option(lpt, 0) != 0) + lpt_en = LPT_LPC_EN; /* enable LPT */ + + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); + + pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); +} + +/* This box has two superios, so enabling serial becomes slightly excessive. + * We disable a lot of stuff to make sure that there are no conflicts between + * the two. Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) +{ + unsigned int port = dev >> 8; + outb(0xaa, port); +} + +void bootblock_mainboard_early_init(void) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(0x2e, 0x00); + + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ + pnp_write_config(dev, 0x02, 0x88); /* UART power on */ + pnp_write_config(dev, 0x03, 0x72); /* Floppy */ + pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ + pnp_write_config(dev, 0x14, 0x03); /* Floppy */ + pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ + pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ + pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ + pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ + pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ + pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ + pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ + /* These are the SMI status registers in the SIO: */ + pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ + + pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ + pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ + pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ + pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ + pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ + pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ + pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ + pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ + pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ + + pnp_exit_ext_func_mode(dev); +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00042220; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0232; + RCBA16(D30IR) = 0x3246; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x3216; + + /* Disable unused devices */ + RCBA32(FD) |= FD_INTLAN; + + /* This should probably go into the ACPI OS Init trap */ + + /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ + RCBA32(0x1e84) = 0x00020001; + RCBA32(0x1e80) = 0x0000fe01; + + /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ + RCBA32(0x1e9c) = 0x000200f0; + RCBA32(0x1e98) = 0x000c0801; +} + +static void init_artec_dongle(void) +{ + /* Enable 4MB decoding */ + outb(0xf1, 0x88); + outb(0xf4, 0x88); +} + +void mainboard_pre_raminit_config(int s3_resume) +{ + init_artec_dongle(); +} diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c deleted file mode 100644 index 388c61a9a6..0000000000 --- a/src/mainboard/roda/rk886ex/romstage.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "option_table.h" - -/* Override the default lpc decode ranges */ -void mainboard_lpc_decode(void) -{ - int lpt_en = 0; - if (read_option(lpt, 0) != 0) - lpt_en = LPT_LPC_EN; /* enable LPT */ - - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); - - pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); -} - -/* This box has two superios, so enabling serial becomes slightly excessive. - * We disable a lot of stuff to make sure that there are no conflicts between - * the two. Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -static inline void pnp_enter_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0x55, port); -} - -static void pnp_exit_ext_func_mode(pnp_devfn_t dev) -{ - unsigned int port = dev >> 8; - outb(0xaa, port); -} - -void mainboard_superio_config(void) -{ - pnp_devfn_t dev; - - dev = PNP_DEV(0x2e, 0x00); - - pnp_enter_ext_func_mode(dev); - pnp_write_config(dev, 0x01, 0x94); /* Extended Parport modes */ - pnp_write_config(dev, 0x02, 0x88); /* UART power on */ - pnp_write_config(dev, 0x03, 0x72); /* Floppy */ - pnp_write_config(dev, 0x04, 0x01); /* EPP + SPP */ - pnp_write_config(dev, 0x14, 0x03); /* Floppy */ - pnp_write_config(dev, 0x20, (0x3f0 >> 2)); /* Floppy */ - pnp_write_config(dev, 0x23, (0x378 >> 2)); /* PP base */ - pnp_write_config(dev, 0x24, (0x3f8 >> 2)); /* UART1 base */ - pnp_write_config(dev, 0x25, (0x2f8 >> 2)); /* UART2 base */ - pnp_write_config(dev, 0x26, (2 << 4) | 0); /* FDC + PP DMA */ - pnp_write_config(dev, 0x27, (6 << 4) | 7); /* FDC + PP DMA */ - pnp_write_config(dev, 0x28, (4 << 4) | 3); /* UART1,2 IRQ */ - /* These are the SMI status registers in the SIO: */ - pnp_write_config(dev, 0x30, (0x600 >> 4)); /* Runtime Register Block Base */ - - pnp_write_config(dev, 0x31, 0x00); /* GPIO1 DIR */ - pnp_write_config(dev, 0x32, 0x00); /* GPIO1 POL */ - pnp_write_config(dev, 0x33, 0x40); /* GPIO2 DIR */ - pnp_write_config(dev, 0x34, 0x00); /* GPIO2 POL */ - pnp_write_config(dev, 0x35, 0xff); /* GPIO3 DIR */ - pnp_write_config(dev, 0x36, 0x00); /* GPIO3 POL */ - pnp_write_config(dev, 0x37, 0xe0); /* GPIO4 DIR */ - pnp_write_config(dev, 0x38, 0x00); /* GPIO4 POL */ - pnp_write_config(dev, 0x39, 0x80); /* GPIO4 POL */ - - pnp_exit_ext_func_mode(dev); -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00042220; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0232; - RCBA16(D30IR) = 0x3246; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3201; - RCBA16(D27IR) = 0x3216; - - /* Disable unused devices */ - RCBA32(FD) |= FD_INTLAN; - - /* This should probably go into the ACPI OS Init trap */ - - /* Set up I/O Trap #0 for 0xfe00 (SMIC) */ - RCBA32(0x1e84) = 0x00020001; - RCBA32(0x1e80) = 0x0000fe01; - - /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */ - RCBA32(0x1e9c) = 0x000200f0; - RCBA32(0x1e98) = 0x000c0801; -} - -static void init_artec_dongle(void) -{ - /* Enable 4MB decoding */ - outb(0xf1, 0x88); - outb(0xf4, 0x88); -} - -void mainboard_pre_raminit_config(int s3_resume) -{ - init_artec_dongle(); -} diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 5aa004d9eb..a0550ec3c7 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -28,7 +28,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select PARALLEL_MP select C_ENVIRONMENT_BOOTBLOCK - select NO_BOOTBLOCK_CONSOLE config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index e9e6f4d094..82f80ff725 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -378,8 +378,6 @@ u32 decode_tseg_size(const u8 esmramc); /* Romstage mainboard callbacks */ /* Optional: Override the default LPC config. */ void mainboard_lpc_decode(void); -/* Optional: Initialize the superio for serial output. */ -void mainboard_superio_config(void); /* Optional: mainboard specific init after console init and before raminit. */ void mainboard_pre_raminit_config(int s3_resume); /* Mainboard specific RCBA init. Happens after raminit. */ diff --git a/src/northbridge/intel/i945/romstage.c b/src/northbridge/intel/i945/romstage.c index c11a78ab0e..479588129d 100644 --- a/src/northbridge/intel/i945/romstage.c +++ b/src/northbridge/intel/i945/romstage.c @@ -28,10 +28,6 @@ __weak void mainboard_lpc_decode(void) { } -__weak void mainboard_superio_config(void) -{ -} - __weak void mainboard_pre_raminit_config(int s3_resume) { } @@ -51,12 +47,7 @@ void mainboard_romstage_entry(void) enable_lapic(); - i82801gx_lpc_setup(); mainboard_lpc_decode(); - mainboard_superio_config(); - - /* Set up the console */ - console_init(); if (MCHBAR16(SSKPD) == 0xCAFE) { system_reset(); diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 68e423af59..9ff0ebc5a1 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -32,6 +32,7 @@ bootblock-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c ramstage-$(CONFIG_USBDEBUG) += usb_debug.c +bootblock-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO) += gpio.c -- cgit v1.2.3