From c5568a145fdd0c9ccf9dff7e3bfb9ffc44328a3f Mon Sep 17 00:00:00 2001 From: Yu-Ping Wu Date: Thu, 24 Oct 2019 15:13:28 +0800 Subject: soc/mediatek/mt8183: Correct continuation line indent BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I9d01d24d3494f2eb28cfb411e13adf3b6717d191 Signed-off-by: Yu-Ping Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/36285 Reviewed-by: Hung-Te Lin Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8183/dramc_pi_basic_api.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src') diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 5901f42acc..d4a1d599fd 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -88,12 +88,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; dramc_dbg("1. OCD DRVP=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + impx_drv, imp_cal_result); if (imp_cal_result == 1 && DRVP_result == 0xff) { DRVP_result = impx_drv; dramc_dbg("1. OCD DRVP calibration OK! DRVP=%d\n", - DRVP_result); + DRVP_result); break; } } @@ -116,12 +116,12 @@ void dramc_sw_impedance_cal(const struct sdram_params *params, u8 term, imp_cal_result = (read32(&ch[0].phy_nao.misc_phy_rgs_cmd) >> 24) & 0x1; dramc_dbg("3. OCD ODTN=%d CALOUT=%d\n", - impx_drv, imp_cal_result); + impx_drv, imp_cal_result); if (imp_cal_result == 0 && ODTN_result == 0xff) { ODTN_result = impx_drv; dramc_dbg("3. OCD ODTN calibration OK! ODTN=%d\n", - ODTN_result); + ODTN_result); break; } } -- cgit v1.2.3