From c4b3903361c4d13242850e99cc382e101f70dccb Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 14 Feb 2021 14:01:55 +0200 Subject: soc/intel: Drop aliases on MMCONF_BASE_ADDRESS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I5ba60c1d8c314d37b4ef71c4613e6e0629da8149 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/50662 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/soc/intel/alderlake/include/soc/iomap.h | 3 --- src/soc/intel/cannonlake/include/soc/iomap.h | 3 --- src/soc/intel/elkhartlake/include/soc/iomap.h | 3 --- src/soc/intel/icelake/include/soc/iomap.h | 3 --- src/soc/intel/jasperlake/include/soc/iomap.h | 3 --- src/soc/intel/tigerlake/include/soc/iomap.h | 3 --- 6 files changed, 18 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/include/soc/iomap.h b/src/soc/intel/alderlake/include/soc/iomap.h index 88fab6f235..23b7c5bc94 100644 --- a/src/soc/intel/alderlake/include/soc/iomap.h +++ b/src/soc/intel/alderlake/include/soc/iomap.h @@ -12,9 +12,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index dc070893c8..e09cec27d6 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -6,9 +6,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 diff --git a/src/soc/intel/elkhartlake/include/soc/iomap.h b/src/soc/intel/elkhartlake/include/soc/iomap.h index 0246673b03..dbbd2292ca 100644 --- a/src/soc/intel/elkhartlake/include/soc/iomap.h +++ b/src/soc/intel/elkhartlake/include/soc/iomap.h @@ -6,9 +6,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 diff --git a/src/soc/intel/icelake/include/soc/iomap.h b/src/soc/intel/icelake/include/soc/iomap.h index 6b82c19ae2..cee9411ae6 100644 --- a/src/soc/intel/icelake/include/soc/iomap.h +++ b/src/soc/intel/icelake/include/soc/iomap.h @@ -6,9 +6,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 diff --git a/src/soc/intel/jasperlake/include/soc/iomap.h b/src/soc/intel/jasperlake/include/soc/iomap.h index 79ffe29f52..eece24aa96 100644 --- a/src/soc/intel/jasperlake/include/soc/iomap.h +++ b/src/soc/intel/jasperlake/include/soc/iomap.h @@ -6,9 +6,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 diff --git a/src/soc/intel/tigerlake/include/soc/iomap.h b/src/soc/intel/tigerlake/include/soc/iomap.h index 6fa29d30cc..cdd370b6c1 100644 --- a/src/soc/intel/tigerlake/include/soc/iomap.h +++ b/src/soc/intel/tigerlake/include/soc/iomap.h @@ -12,9 +12,6 @@ /* * Memory-mapped I/O registers. */ -#define MCFG_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MCFG_BASE_SIZE 0x4000000 - #define PCH_PRESERVED_BASE_ADDRESS 0xfc800000 #define PCH_PRESERVED_BASE_SIZE 0x02000000 -- cgit v1.2.3