From c1d1dddbccba1d1468b75bc8d4685bd8e7184264 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Tue, 24 Nov 2020 13:49:11 +0100 Subject: mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- .../supermicro/x11-lga1151-series/Makefile.inc | 7 +- .../supermicro/x11-lga1151-series/bootblock.c | 13 +- .../x11-lga1151-series/include/mainboard/gpio.h | 9 + .../supermicro/x11-lga1151-series/mainboard.c | 5 +- .../x11-lga1151-series/variants/x11ssh-f/gpio.c | 230 +++++++++++++++++++ .../variants/x11ssh-f/gpio_early.c | 22 ++ .../variants/x11ssh-f/include/variant/gpio.h | 242 -------------------- .../x11-lga1151-series/variants/x11ssh-tf/gpio.c | 230 +++++++++++++++++++ .../variants/x11ssh-tf/gpio_early.c | 22 ++ .../variants/x11ssh-tf/include/variant/gpio.h | 242 -------------------- .../x11-lga1151-series/variants/x11ssm-f/gpio.c | 236 ++++++++++++++++++++ .../variants/x11ssm-f/gpio_early.c | 22 ++ .../variants/x11ssm-f/include/variant/gpio.h | 248 --------------------- 13 files changed, 779 insertions(+), 749 deletions(-) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c delete mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c delete mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c delete mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h (limited to 'src') diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index f9b4e9890b..035dd281bb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -1,10 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c ramstage-y += mainboard.c - -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +ramstage-y += variants/$(VARIANT_DIR)/gpio.c subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 3e5751c3d7..b137c75589 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -1,20 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include +#include #include #include #include -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - static void early_config_superio(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); @@ -23,6 +14,6 @@ static void early_config_superio(void) void bootblock_mainboard_early_init(void) { - early_config_gpio(); + mainboard_configure_early_gpios(); early_config_superio(); } diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h new file mode 100644 index 0000000000..c6393beebb --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 1377a874fe..0f8dbed2ed 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -2,8 +2,7 @@ #include #include -#include -#include +#include __weak void variant_mainboard_init(void *chip_info) { @@ -12,7 +11,7 @@ __weak void variant_mainboard_init(void *chip_info) static void mainboard_chip_init(void *chip_info) { /* do common init */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); /* do variant init */ variant_mainboard_init(chip_info); diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c new file mode 100644 index 0000000000..e37e008285 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_NC(GPP_D22, NONE), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_NC(GPP_F9, NONE), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_NC(GPP_G12, NONE), + PAD_NC(GPP_G13, NONE), + PAD_NC(GPP_G14, NONE), + PAD_NC(GPP_G15, NONE), + PAD_NC(GPP_G16, NONE), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_NC(GPP_H1, NONE), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_NC(GPP_H4, NONE), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c new file mode 100644 index 0000000000..3ea21e0321 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h deleted file mode 100644 index 449349dc6c..0000000000 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _GPIO_X11SSH_F_H -#define _GPIO_X11SSH_F_H - -#include -#include - -static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), - PAD_NC(GPP_A12, NONE), - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - PAD_NC(GPP_A17, NONE), - PAD_NC(GPP_A18, NONE), - /* GPP_A19 - RESERVED */ - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), - PAD_CFG_GPO(GPP_B0, 1, DEEP), - PAD_CFG_GPO(GPP_B1, 1, DEEP), - PAD_NC(GPP_B2, NONE), - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_NC(GPP_B9, NONE), - PAD_NC(GPP_B10, NONE), - PAD_CFG_GPO(GPP_B11, 0, DEEP), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), - PAD_NC(GPP_B18, NONE), - PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO(GPP_B20, 1, PLTRST), - PAD_NC(GPP_B21, NONE), - PAD_NC(GPP_B22, NONE), - PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), - - /* GPIO Group GPP_C */ - /* GPP_C0 - RESERVED */ - /* GPP_C1 - RESERVED */ - PAD_NC(GPP_C2, NONE), - /* GPP_C3 - RESERVED */ - /* GPP_C4 - RESERVED */ - PAD_CFG_GPO(GPP_C5, 1, DEEP), - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - PAD_NC(GPP_C8, NONE), - PAD_NC(GPP_C9, NONE), - PAD_NC(GPP_C10, NONE), - PAD_NC(GPP_C11, NONE), - PAD_NC(GPP_C12, NONE), - PAD_NC(GPP_C13, NONE), - PAD_NC(GPP_C14, NONE), - PAD_NC(GPP_C15, NONE), - PAD_NC(GPP_C16, NONE), - PAD_NC(GPP_C17, NONE), - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_NC(GPP_C20, NONE), - PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), - PAD_NC(GPP_C23, NONE), - - /* GPIO Group GPP_D */ - PAD_NC(GPP_D0, NONE), - PAD_CFG_GPO(GPP_D1, 1, DEEP), - PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), - PAD_NC(GPP_D3, NONE), - PAD_CFG_GPO(GPP_D4, 0, PLTRST), - PAD_NC(GPP_D5, NONE), - PAD_NC(GPP_D6, NONE), - PAD_NC(GPP_D7, NONE), - PAD_NC(GPP_D8, NONE), - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D12, NONE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), - PAD_CFG_GPO(GPP_D18, 1, PLTRST), - PAD_CFG_GPO(GPP_D19, 1, PLTRST), - PAD_NC(GPP_D20, NONE), - PAD_CFG_GPO(GPP_D21, 0, DEEP), - PAD_NC(GPP_D22, NONE), - PAD_NC(GPP_D23, NONE), - - /* GPIO Group GPP_E */ - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_NC(GPP_E3, NONE), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), - PAD_NC(GPP_E7, NONE), - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - /* GPIO Group GPP_F */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), - PAD_CFG_GPO(GPP_F6, 1, PLTRST), - PAD_CFG_GPO(GPP_F7, 1, PLTRST), - PAD_CFG_GPO(GPP_F8, 1, PLTRST), - PAD_NC(GPP_F9, NONE), - PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - PAD_NC(GPP_F14, NONE), - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F19, NONE), - PAD_NC(GPP_F20, NONE), - PAD_NC(GPP_F21, NONE), - PAD_NC(GPP_F22, NONE), - PAD_CFG_GPO(GPP_F23, 0, RSMRST), - PAD_NC(GPP_G0, NONE), - PAD_NC(GPP_G1, NONE), - PAD_NC(GPP_G2, NONE), - PAD_NC(GPP_G3, NONE), - PAD_NC(GPP_G4, NONE), - PAD_NC(GPP_G5, NONE), - PAD_NC(GPP_G6, NONE), - PAD_NC(GPP_G7, NONE), - PAD_NC(GPP_G8, NONE), - PAD_NC(GPP_G9, NONE), - PAD_NC(GPP_G10, NONE), - PAD_NC(GPP_G11, NONE), - PAD_NC(GPP_G12, NONE), - PAD_NC(GPP_G13, NONE), - PAD_NC(GPP_G14, NONE), - PAD_NC(GPP_G15, NONE), - PAD_NC(GPP_G16, NONE), - PAD_NC(GPP_G17, NONE), - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), - PAD_NC(GPP_G20, NONE), - PAD_NC(GPP_G21, NONE), - PAD_NC(GPP_G22, NONE), - PAD_NC(GPP_G23, NONE), - PAD_CFG_GPO(GPP_H0, 1, DEEP), - PAD_NC(GPP_H1, NONE), - PAD_CFG_GPO(GPP_H2, 1, DEEP), - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), - PAD_NC(GPP_H4, NONE), - PAD_CFG_GPO(GPP_H5, 1, PLTRST), - PAD_CFG_GPO(GPP_H6, 1, PLTRST), - PAD_CFG_GPO(GPP_H7, 1, PLTRST), - PAD_CFG_GPO(GPP_H8, 1, PLTRST), - PAD_CFG_GPO(GPP_H9, 1, PLTRST), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - PAD_NC(GPP_H12, NONE), - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), - PAD_NC(GPP_H15, NONE), - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - PAD_NC(GPP_H18, NONE), - PAD_CFG_GPO(GPP_H19, 1, PLTRST), - PAD_CFG_GPO(GPP_H20, 1, PLTRST), - PAD_CFG_GPO(GPP_H21, 1, PLTRST), - PAD_CFG_GPO(GPP_H22, 1, PLTRST), - PAD_CFG_GPO(GPP_H23, 1, PLTRST), - - /* GPIO Group GPD */ - PAD_NC(GPD0, NONE), - PAD_NC(GPD1, NONE), - PAD_CFG_NF(GPD2, NONE, PWROK, NF1), - PAD_CFG_NF(GPD3, NONE, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_NC(GPD7, NONE), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_NC(GPD9, NONE), - PAD_NC(GPD10, NONE), - PAD_NC(GPD11, NONE), - - /* GPIO Group GPP_I */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), - PAD_NC(GPP_I4, NONE), - PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), -}; - -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSH_F_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c new file mode 100644 index 0000000000..06d3bd43c3 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c @@ -0,0 +1,230 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_A12, 1, PLTRST), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + PAD_CFG_GPO(GPP_B0, 1, DEEP), + PAD_CFG_GPO(GPP_B1, 1, DEEP), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO(GPP_B11, 0, DEEP), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + /* GPP_C0 - RESERVED */ + /* GPP_C1 - RESERVED */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - RESERVED */ + /* GPP_C4 - RESERVED */ + PAD_CFG_GPO(GPP_C5, 1, DEEP), + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO(GPP_D18, 1, PLTRST), + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO(GPP_D21, 0, DEEP), + PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO(GPP_F6, 1, PLTRST), + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + PAD_CFG_GPO(GPP_F8, 1, PLTRST), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO(GPP_F23, 0, RSMRST), + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + PAD_CFG_GPO(GPP_H0, 1, DEEP), + PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H2, 1, DEEP), + PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + PAD_CFG_GPO(GPP_H5, 1, PLTRST), + PAD_CFG_GPO(GPP_H6, 1, PLTRST), + PAD_CFG_GPO(GPP_H7, 1, PLTRST), + PAD_CFG_GPO(GPP_H8, 1, PLTRST), + PAD_CFG_GPO(GPP_H9, 1, PLTRST), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO(GPP_H19, 1, PLTRST), + PAD_CFG_GPO(GPP_H20, 1, PLTRST), + PAD_CFG_GPO(GPP_H21, 1, PLTRST), + PAD_CFG_GPO(GPP_H22, 1, PLTRST), + PAD_CFG_GPO(GPP_H23, 1, PLTRST), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c new file mode 100644 index 0000000000..3ea21e0321 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h deleted file mode 100644 index 486caf4185..0000000000 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _GPIO_X11SSH_TF_H -#define _GPIO_X11SSH_TF_H - -#include -#include - -static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), - PAD_CFG_GPO(GPP_A12, 1, PLTRST), - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - PAD_NC(GPP_A17, NONE), - PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), - /* GPP_A19 - RESERVED */ - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), - PAD_CFG_GPO(GPP_B0, 1, DEEP), - PAD_CFG_GPO(GPP_B1, 1, DEEP), - PAD_NC(GPP_B2, NONE), - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_NC(GPP_B9, NONE), - PAD_NC(GPP_B10, NONE), - PAD_CFG_GPO(GPP_B11, 0, DEEP), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), - PAD_NC(GPP_B18, NONE), - PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO(GPP_B20, 1, PLTRST), - PAD_NC(GPP_B21, NONE), - PAD_NC(GPP_B22, NONE), - PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), - - /* GPIO Group GPP_C */ - /* GPP_C0 - RESERVED */ - /* GPP_C1 - RESERVED */ - PAD_NC(GPP_C2, NONE), - /* GPP_C3 - RESERVED */ - /* GPP_C4 - RESERVED */ - PAD_CFG_GPO(GPP_C5, 1, DEEP), - /* GPP_C6 - RESERVED */ - /* GPP_C7 - RESERVED */ - PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), - PAD_NC(GPP_C11, NONE), - PAD_NC(GPP_C12, NONE), - PAD_NC(GPP_C13, NONE), - PAD_NC(GPP_C14, NONE), - PAD_NC(GPP_C15, NONE), - PAD_NC(GPP_C16, NONE), - PAD_NC(GPP_C17, NONE), - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_NC(GPP_C20, NONE), - PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), - PAD_NC(GPP_C23, NONE), - - /* GPIO Group GPP_D */ - PAD_NC(GPP_D0, NONE), - PAD_CFG_GPO(GPP_D1, 1, DEEP), - PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), - PAD_NC(GPP_D3, NONE), - PAD_CFG_GPO(GPP_D4, 0, PLTRST), - PAD_NC(GPP_D5, NONE), - PAD_NC(GPP_D6, NONE), - PAD_NC(GPP_D7, NONE), - PAD_NC(GPP_D8, NONE), - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D12, NONE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), - PAD_CFG_GPO(GPP_D18, 1, PLTRST), - PAD_CFG_GPO(GPP_D19, 1, PLTRST), - PAD_NC(GPP_D20, NONE), - PAD_CFG_GPO(GPP_D21, 0, DEEP), - PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), - PAD_NC(GPP_D23, NONE), - - /* GPIO Group GPP_E */ - PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_NC(GPP_E3, NONE), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), - PAD_NC(GPP_E7, NONE), - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - /* GPIO Group GPP_F */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), - PAD_CFG_GPO(GPP_F6, 1, PLTRST), - PAD_CFG_GPO(GPP_F7, 1, PLTRST), - PAD_CFG_GPO(GPP_F8, 1, PLTRST), - PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - PAD_NC(GPP_F14, NONE), - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F19, NONE), - PAD_NC(GPP_F20, NONE), - PAD_NC(GPP_F21, NONE), - PAD_NC(GPP_F22, NONE), - PAD_CFG_GPO(GPP_F23, 0, RSMRST), - PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), - PAD_NC(GPP_G4, NONE), - PAD_NC(GPP_G5, NONE), - PAD_NC(GPP_G6, NONE), - PAD_NC(GPP_G7, NONE), - PAD_NC(GPP_G8, NONE), - PAD_NC(GPP_G9, NONE), - PAD_NC(GPP_G10, NONE), - PAD_NC(GPP_G11, NONE), - PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), - PAD_NC(GPP_G17, NONE), - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), - PAD_NC(GPP_G20, NONE), - PAD_NC(GPP_G21, NONE), - PAD_NC(GPP_G22, NONE), - PAD_NC(GPP_G23, NONE), - PAD_CFG_GPO(GPP_H0, 1, DEEP), - PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_H2, 1, DEEP), - PAD_CFG_NF(GPP_H3, NONE, DEEP, NF1), - PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), - PAD_CFG_GPO(GPP_H5, 1, PLTRST), - PAD_CFG_GPO(GPP_H6, 1, PLTRST), - PAD_CFG_GPO(GPP_H7, 1, PLTRST), - PAD_CFG_GPO(GPP_H8, 1, PLTRST), - PAD_CFG_GPO(GPP_H9, 1, PLTRST), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - PAD_NC(GPP_H12, NONE), - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), - PAD_NC(GPP_H15, NONE), - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - PAD_NC(GPP_H18, NONE), - PAD_CFG_GPO(GPP_H19, 1, PLTRST), - PAD_CFG_GPO(GPP_H20, 1, PLTRST), - PAD_CFG_GPO(GPP_H21, 1, PLTRST), - PAD_CFG_GPO(GPP_H22, 1, PLTRST), - PAD_CFG_GPO(GPP_H23, 1, PLTRST), - - /* GPIO Group GPD */ - PAD_NC(GPD0, NONE), - PAD_NC(GPD1, NONE), - PAD_CFG_NF(GPD2, NONE, PWROK, NF1), - PAD_CFG_NF(GPD3, NONE, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_NC(GPD7, NONE), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_NC(GPD9, NONE), - PAD_NC(GPD10, NONE), - PAD_NC(GPD11, NONE), - - /* GPIO Group GPP_I */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), - PAD_NC(GPP_I4, NONE), - PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), -}; - -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSH_TF_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c new file mode 100644 index 0000000000..dc41573224 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -0,0 +1,236 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_NC(GPP_A17, NONE), + PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), + /* GPP_A19 - RESERVED */ + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* GPIO Group GPP_B */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), + + /* GPIO Group GPP_C */ + // PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + // PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + // PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), + // PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + // PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_C23, NONE), + + /* GPIO Group GPP_D */ + PAD_NC(GPP_D0, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), + PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), + PAD_NC(GPP_D3, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), + PAD_NC(GPP_D20, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), + PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), + PAD_NC(GPP_D23, NONE), + + /* GPIO Group GPP_E */ + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), + PAD_NC(GPP_E7, NONE), + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), + + /* GPIO Group GPP_F */ + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), + PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + PAD_NC(GPP_F14, NONE), + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), + + /* GPIO Group GPP_G */ + PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), + PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), + PAD_NC(GPP_G4, NONE), + PAD_NC(GPP_G5, NONE), + PAD_NC(GPP_G6, NONE), + PAD_NC(GPP_G7, NONE), + PAD_NC(GPP_G8, NONE), + PAD_NC(GPP_G9, NONE), + PAD_NC(GPP_G10, NONE), + PAD_NC(GPP_G11, NONE), + PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), + PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), + PAD_NC(GPP_G17, NONE), + PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), + PAD_NC(GPP_G20, NONE), + PAD_NC(GPP_G21, NONE), + PAD_NC(GPP_G22, NONE), + PAD_NC(GPP_G23, NONE), + + /* GPIO Group GPP_H */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), + PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), + PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_NC(GPP_H12, NONE), + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_NC(GPP_H18, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), + PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), + + /* GPIO Group GPP_I */ + PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), + PAD_NC(GPP_I4, NONE), + PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + + /* GPIO Group GPD */ + PAD_NC(GPD0, NONE), + PAD_NC(GPD1, NONE), + PAD_CFG_NF(GPD2, NONE, PWROK, NF1), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + PAD_NC(GPD9, NONE), + PAD_NC(GPD10, NONE), + PAD_NC(GPD11, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c new file mode 100644 index 0000000000..3ea21e0321 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h deleted file mode 100644 index 8c9d08e5ef..0000000000 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ /dev/null @@ -1,248 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _GPIO_X11SSM_F_H -#define _GPIO_X11SSM_F_H - -#include -#include - -static const struct pad_config gpio_table[] = { - /* GPIO Group GPP_A */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1), - PAD_NC(GPP_A12, NONE), - PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - PAD_NC(GPP_A17, NONE), - PAD_CFG_GPI_INT(GPP_A18, NONE, PLTRST, OFF), - /* GPP_A19 - RESERVED */ - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), - - /* GPIO Group GPP_B */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_B0, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B1, 1, DEEP, NONE), - PAD_NC(GPP_B2, NONE), - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_NC(GPP_B8, NONE), - PAD_NC(GPP_B9, NONE), - PAD_NC(GPP_B10, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B11, 0, DEEP, NONE), - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), - PAD_NC(GPP_B18, NONE), - PAD_NC(GPP_B19, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_B20, 1, PLTRST, NONE), - PAD_NC(GPP_B21, NONE), - PAD_NC(GPP_B22, NONE), - PAD_CFG_NF(GPP_B23, NONE, DEEP, NF2), - - /* GPIO Group GPP_C */ - // PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - // PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - PAD_NC(GPP_C2, NONE), - // PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - // PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - PAD_CFG_GPO_GPIO_DRIVER(GPP_C5, 1, DEEP, NONE), - // PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), - // PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), - PAD_CFG_GPI_INT(GPP_C8, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C9, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_C10, NONE, PLTRST, OFF), - PAD_NC(GPP_C11, NONE), - PAD_NC(GPP_C12, NONE), - PAD_NC(GPP_C13, NONE), - PAD_NC(GPP_C14, NONE), - PAD_NC(GPP_C15, NONE), - PAD_NC(GPP_C16, NONE), - PAD_NC(GPP_C17, NONE), - PAD_NC(GPP_C18, NONE), - PAD_NC(GPP_C19, NONE), - PAD_NC(GPP_C20, NONE), - PAD_NC(GPP_C21, NONE), - PAD_CFG_GPI_SMI(GPP_C22, UP_20K, DEEP, EDGE_SINGLE, NONE), - PAD_NC(GPP_C23, NONE), - - /* GPIO Group GPP_D */ - PAD_NC(GPP_D0, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D1, 1, DEEP, NONE), - PAD_CFG_GPI_NMI(GPP_D2, UP_20K, DEEP, EDGE_SINGLE, NONE), - PAD_NC(GPP_D3, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D4, 0, PLTRST, NONE), - PAD_NC(GPP_D5, NONE), - PAD_NC(GPP_D6, NONE), - PAD_NC(GPP_D7, NONE), - PAD_NC(GPP_D8, NONE), - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D12, NONE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D18, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D19, 1, PLTRST, NONE), - PAD_NC(GPP_D20, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_D21, 0, DEEP, NONE), - PAD_CFG_GPI_INT(GPP_D22, NONE, RSMRST, OFF), - PAD_NC(GPP_D23, NONE), - - /* GPIO Group GPP_E */ - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_NC(GPP_E3, NONE), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_CFG_GPI_NMI(GPP_E6, UP_20K, PLTRST, EDGE_SINGLE, NONE), - PAD_NC(GPP_E7, NONE), - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), - - /* GPIO Group GPP_F */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), - PAD_CFG_GPI_APIC_HIGH(GPP_F5, NONE, PLTRST), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F8, 1, PLTRST, NONE), - PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, OFF), - PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - PAD_NC(GPP_F14, NONE), - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F19, NONE), - PAD_NC(GPP_F20, NONE), - PAD_NC(GPP_F21, NONE), - PAD_NC(GPP_F22, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_F23, 0, RSMRST, NONE), - - /* GPIO Group GPP_G */ - PAD_CFG_GPI_INT(GPP_G0, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G1, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G2, NONE, DEEP, OFF), - PAD_CFG_GPI_INT(GPP_G3, NONE, DEEP, OFF), - PAD_NC(GPP_G4, NONE), - PAD_NC(GPP_G5, NONE), - PAD_NC(GPP_G6, NONE), - PAD_NC(GPP_G7, NONE), - PAD_NC(GPP_G8, NONE), - PAD_NC(GPP_G9, NONE), - PAD_NC(GPP_G10, NONE), - PAD_NC(GPP_G11, NONE), - PAD_CFG_GPI_INT(GPP_G12, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G13, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G14, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G15, NONE, PLTRST, OFF), - PAD_CFG_GPI_INT(GPP_G16, NONE, PLTRST, OFF), - PAD_NC(GPP_G17, NONE), - PAD_CFG_NF(GPP_G18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), - PAD_NC(GPP_G20, NONE), - PAD_NC(GPP_G21, NONE), - PAD_NC(GPP_G22, NONE), - PAD_NC(GPP_G23, NONE), - - /* GPIO Group GPP_H */ - PAD_CFG_GPO_GPIO_DRIVER(GPP_H0, 1, DEEP, NONE), - PAD_CFG_GPI_INT(GPP_H1, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H2, 1, DEEP, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H3, 1, DEEP, NONE), - PAD_CFG_GPI_INT(GPP_H4, NONE, PLTRST, OFF), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H5, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H6, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H7, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H8, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H9, 1, PLTRST, NONE), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - PAD_NC(GPP_H12, NONE), - PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H14, NONE, DEEP, NF1), - PAD_NC(GPP_H15, NONE), - PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), - PAD_NC(GPP_H18, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H19, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H20, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H21, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H22, 1, PLTRST, NONE), - PAD_CFG_GPO_GPIO_DRIVER(GPP_H23, 1, PLTRST, NONE), - - /* GPIO Group GPP_I */ - PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), - PAD_NC(GPP_I4, NONE), - PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), - - /* GPIO Group GPD */ - PAD_NC(GPD0, NONE), - PAD_NC(GPD1, NONE), - PAD_CFG_NF(GPD2, NONE, PWROK, NF1), - PAD_CFG_NF(GPD3, NONE, PWROK, NF1), - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), - PAD_NC(GPD7, NONE), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), - PAD_NC(GPD9, NONE), - PAD_NC(GPD10, NONE), - PAD_NC(GPD11, NONE), -}; - -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSM_F_H */ -- cgit v1.2.3