From c1bf8ccdbc2aa2d50d52b049aa5875ff7064c5fd Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 28 Jan 2019 12:11:06 +0530 Subject: mb/intel/icelake_rvp/../icl_y: Enable SaGv This patch enables SaGv on Intel ICL-Y RVP board. TEST=Able to build and boot to Chrome OS. Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/31119 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Duncan Laurie --- src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 0972c29e12..4f4130853e 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -13,7 +13,7 @@ chip soc/intel/icelake register "gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" -- cgit v1.2.3