From c0982abf86a6312e2572cc0225bbfe702c7ff2bd Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 23 Sep 2021 15:28:51 +0200 Subject: soc/amd/common/block: move binaryPI S3 block into PI block The code in soc/amd/common/block/s3 is specific to the AMD binaryPI coreboot integration, so move the code to soc/amd/common/block/pi. This drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking process, we don't lose support for any working configuration by only having one Kconfig option for both parts. Signed-off-by: Felix Held Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/soc/amd/common/block/pi/Kconfig | 5 +- src/soc/amd/common/block/pi/Makefile.inc | 2 + src/soc/amd/common/block/pi/s3_resume.c | 80 ++++++++++++++++++++++++++++++++ src/soc/amd/common/block/s3/Kconfig | 7 --- src/soc/amd/common/block/s3/Makefile.inc | 6 --- src/soc/amd/common/block/s3/s3_resume.c | 80 -------------------------------- src/soc/amd/stoneyridge/Kconfig | 1 - 7 files changed, 86 insertions(+), 95 deletions(-) create mode 100644 src/soc/amd/common/block/pi/s3_resume.c delete mode 100644 src/soc/amd/common/block/s3/Kconfig delete mode 100644 src/soc/amd/common/block/s3/Makefile.inc delete mode 100644 src/soc/amd/common/block/s3/s3_resume.c (limited to 'src') diff --git a/src/soc/amd/common/block/pi/Kconfig b/src/soc/amd/common/block/pi/Kconfig index d2a2a6ad9b..b872c13484 100644 --- a/src/soc/amd/common/block/pi/Kconfig +++ b/src/soc/amd/common/block/pi/Kconfig @@ -1,9 +1,12 @@ config SOC_AMD_COMMON_BLOCK_PI bool + depends on SOC_AMD_COMMON_BLOCK_ACPI + select CACHE_MRC_SETTINGS select HAVE_DEBUG_RAM_SETUP + select MRC_WRITE_NV_LATE help This option builds functions that interface AMD's AGESA reference - code packaged in the binaryPI form. + code packaged in the binaryPI form and S3-related functionality. if SOC_AMD_COMMON_BLOCK_PI diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index 7b5d73af9c..59f075ddd7 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -5,6 +5,7 @@ romstage-y += def_callouts.c romstage-y += heapmanager.c romstage-y += image.c romstage-y += refcode_loader.c +romstage-y += s3_resume.c ramstage-y += agesawrapper.c ramstage-y += amd_late_init.c @@ -13,5 +14,6 @@ ramstage-y += def_callouts.c ramstage-y += heapmanager.c ramstage-y += image.c ramstage-y += refcode_loader.c +ramstage-y += s3_resume.c endif # CONFIG_SOC_AMD_COMMON_BLOCK_PI diff --git a/src/soc/amd/common/block/pi/s3_resume.c b/src/soc/amd/common/block/pi/s3_resume.c new file mode 100644 index 0000000000..2094931dca --- /dev/null +++ b/src/soc/amd/common/block/pi/s3_resume.c @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Training data versioning is not supported or tracked. */ +#define DEFAULT_MRC_VERSION 0 + +static void __noreturn reboot_from_resume(const char *message) +{ + printk(BIOS_ERR, "%s", message); + set_pm1cnt_s5(); + board_reset(); +} + +AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) +{ + void *base; + size_t size; + int i; + uint32_t erased = 0xffffffff; + + base = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, + DEFAULT_MRC_VERSION, + &size); + if (!base || !size) + reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); + + /* Read 16 bytes to infer if the NV has been erased from flash. */ + for (i = 0; i < 4; i++) + erased &= read32((uint32_t *)base + i); + if (erased == 0xffffffff) + reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); + + dataBlock->NvStorage = base; + dataBlock->NvStorageSize = size; + printk(BIOS_SPEW, "S3 NV data @%p, 0x%0zx bytes\n", + dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); + + return AGESA_SUCCESS; +} + +AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) +{ + void *base = NULL; + size_t size = 0; + + stage_cache_get_raw(STAGE_S3_DATA, &base, &size); + if (!base || !size) { + printk(BIOS_ERR, "Error: S3 volatile data not found\n"); + return AGESA_FATAL; + } + + dataBlock->VolatileStorage = base; + dataBlock->VolatileStorageSize = size; + printk(BIOS_SPEW, "S3 volatile data @%p, 0x%0zx bytes\n", + dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; +} + +AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock) +{ + if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, + dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { + printk(BIOS_ERR, "Failed to stash MRC data\n"); + return AGESA_CRITICAL; + } + + stage_cache_add_raw(STAGE_S3_DATA, dataBlock->VolatileStorage, + dataBlock->VolatileStorageSize); + + return AGESA_SUCCESS; +} diff --git a/src/soc/amd/common/block/s3/Kconfig b/src/soc/amd/common/block/s3/Kconfig deleted file mode 100644 index 797a59864a..0000000000 --- a/src/soc/amd/common/block/s3/Kconfig +++ /dev/null @@ -1,7 +0,0 @@ -config SOC_AMD_COMMON_BLOCK_S3 - bool - depends on SOC_AMD_COMMON_BLOCK_ACPI - select CACHE_MRC_SETTINGS - select MRC_WRITE_NV_LATE - help - Select this option to add S3 related functions to the build. diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc deleted file mode 100644 index 03395eca9c..0000000000 --- a/src/soc/amd/common/block/s3/Makefile.inc +++ /dev/null @@ -1,6 +0,0 @@ -ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y) - -romstage-y += s3_resume.c -ramstage-y += s3_resume.c - -endif # CONFIG_SOC_AMD_COMMON_BLOCK_S3 diff --git a/src/soc/amd/common/block/s3/s3_resume.c b/src/soc/amd/common/block/s3/s3_resume.c deleted file mode 100644 index 2094931dca..0000000000 --- a/src/soc/amd/common/block/s3/s3_resume.c +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include - -/* Training data versioning is not supported or tracked. */ -#define DEFAULT_MRC_VERSION 0 - -static void __noreturn reboot_from_resume(const char *message) -{ - printk(BIOS_ERR, "%s", message); - set_pm1cnt_s5(); - board_reset(); -} - -AGESA_STATUS OemInitResume(S3_DATA_BLOCK *dataBlock) -{ - void *base; - size_t size; - int i; - uint32_t erased = 0xffffffff; - - base = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, - DEFAULT_MRC_VERSION, - &size); - if (!base || !size) - reboot_from_resume("Error: S3 NV data not found, rebooting.\n"); - - /* Read 16 bytes to infer if the NV has been erased from flash. */ - for (i = 0; i < 4; i++) - erased &= read32((uint32_t *)base + i); - if (erased == 0xffffffff) - reboot_from_resume("Error: S3 NV data invalid, rebooting.\n"); - - dataBlock->NvStorage = base; - dataBlock->NvStorageSize = size; - printk(BIOS_SPEW, "S3 NV data @%p, 0x%0zx bytes\n", - dataBlock->NvStorage, (size_t)dataBlock->NvStorageSize); - - return AGESA_SUCCESS; -} - -AGESA_STATUS OemS3LateRestore(S3_DATA_BLOCK *dataBlock) -{ - void *base = NULL; - size_t size = 0; - - stage_cache_get_raw(STAGE_S3_DATA, &base, &size); - if (!base || !size) { - printk(BIOS_ERR, "Error: S3 volatile data not found\n"); - return AGESA_FATAL; - } - - dataBlock->VolatileStorage = base; - dataBlock->VolatileStorageSize = size; - printk(BIOS_SPEW, "S3 volatile data @%p, 0x%0zx bytes\n", - dataBlock->VolatileStorage, (size_t)dataBlock->VolatileStorageSize); - - return AGESA_SUCCESS; -} - -AGESA_STATUS OemS3Save(S3_DATA_BLOCK *dataBlock) -{ - if (mrc_cache_stash_data(MRC_TRAINING_DATA, DEFAULT_MRC_VERSION, - dataBlock->NvStorage, dataBlock->NvStorageSize) < 0) { - printk(BIOS_ERR, "Failed to stash MRC data\n"); - return AGESA_CRITICAL; - } - - stage_cache_add_raw(STAGE_S3_DATA, dataBlock->VolatileStorage, - dataBlock->VolatileStorageSize); - - return AGESA_SUCCESS; -} diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 08b2ef4db6..b07b4c9181 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -39,7 +39,6 @@ config CPU_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_PI select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PSP_GEN1 - select SOC_AMD_COMMON_BLOCK_S3 select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI -- cgit v1.2.3