From c07d2e5a9b8d9e5c9db183ae243b4a92dba67d95 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sat, 5 Jun 2021 19:58:58 +0530 Subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset The patch corrects TCSS XHCI Port status offset and CPU USB2 port count. The information is captured from the ADL-P Processor EDS Volume 2b of 2 (DOC ID:619503). BUG=None TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55230 Tested-by: build bot (Jenkins) Reviewed-by: Ronak Kanabar Reviewed-by: Subrata Banik Reviewed-by: Maulik V Vaghela --- src/soc/intel/alderlake/xhci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/xhci.c b/src/soc/intel/alderlake/xhci.c index 922633667f..36d1491faa 100644 --- a/src/soc/intel/alderlake/xhci.c +++ b/src/soc/intel/alderlake/xhci.c @@ -15,8 +15,8 @@ #define PCH_XHCI_USB3_PORT_NUM 4 #define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480 -#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x540 -#define TCSS_XHCI_USB2_PORT_NUM 10 +#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490 +#define TCSS_XHCI_USB2_PORT_NUM 0 #define TCSS_XHCI_USB3_PORT_NUM 4 static const struct xhci_usb_info usb_info = { -- cgit v1.2.3