From c077f4a84cac69d2bf6ff71d7a4065bfff614a69 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 24 Jun 2020 20:43:22 +0200 Subject: mb/amd/mandolin: make mandolin a variant of itself A follow-up patch will add Cereme which is a Mandolin variant. Beware that the name of the EC firmware image is changed from mchp.bin to EC_mandolin.bin. TEST=Mandolin still boots into Linux live system. Change-Id: Ifee91306756f8a4152a6a0224e172dae7eac8f7a Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/42785 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/Kconfig | 22 ++- src/mainboard/amd/mandolin/Makefile.inc | 6 +- src/mainboard/amd/mandolin/devicetree.cb | 85 --------- src/mainboard/amd/mandolin/early_gpio.c | 36 ---- src/mainboard/amd/mandolin/gpio.c | 36 ---- src/mainboard/amd/mandolin/mandolin.fmd | 8 - src/mainboard/amd/mandolin/port_descriptors.c | 208 --------------------- .../amd/mandolin/variants/mandolin/board.fmd | 8 + .../amd/mandolin/variants/mandolin/devicetree.cb | 85 +++++++++ .../amd/mandolin/variants/mandolin/early_gpio.c | 36 ++++ .../amd/mandolin/variants/mandolin/gpio.c | 36 ++++ .../mandolin/variants/mandolin/port_descriptors.c | 208 +++++++++++++++++++++ 12 files changed, 391 insertions(+), 383 deletions(-) delete mode 100644 src/mainboard/amd/mandolin/devicetree.cb delete mode 100644 src/mainboard/amd/mandolin/early_gpio.c delete mode 100644 src/mainboard/amd/mandolin/gpio.c delete mode 100644 src/mainboard/amd/mandolin/mandolin.fmd delete mode 100644 src/mainboard/amd/mandolin/port_descriptors.c create mode 100644 src/mainboard/amd/mandolin/variants/mandolin/board.fmd create mode 100644 src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb create mode 100644 src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c create mode 100644 src/mainboard/amd/mandolin/variants/mandolin/gpio.c create mode 100644 src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c (limited to 'src') diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 42ac9e5c6c..599e64ab83 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -7,13 +7,13 @@ config BOARD_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME config FMDFILE string - default "src/mainboard/amd/mandolin/mandolin.fmd" + default "src/mainboard/amd/mandolin/variants/\$(CONFIG_VARIANT_DIR)/board.fmd" config AMD_LPC_DEBUG_CARD bool "Enable LPC-Serial debug card on the debug header" @@ -28,15 +28,23 @@ config AMD_LPC_DEBUG_CARD config CBFS_SIZE hex - default 0x7cf000 # Maximum size for the Mandolin FMAP + default 0x7cf000 if BOARD_AMD_MANDOLIN # Maximum size for the Mandolin FMAP config MAINBOARD_DIR string default "amd/mandolin" +config VARIANT_DIR + string + default "mandolin" if BOARD_AMD_MANDOLIN + config MAINBOARD_PART_NUMBER string - default "MANDOLIN" + default "MANDOLIN" if BOARD_AMD_MANDOLIN + +config DEVICETREE + string + default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" config MAX_CPUS int @@ -48,7 +56,7 @@ config ONBOARD_VGA_IS_PRIMARY config AMD_FWM_POSITION_INDEX int - default 3 + default 3 if BOARD_AMD_MANDOLIN help TODO: might need to be adapted for better placement of files in cbfs @@ -59,7 +67,7 @@ config MANDOLIN_HAVE_MCHP_FW config MANDOLIN_MCHP_FW_FILE string depends on MANDOLIN_HAVE_MCHP_FW - default "3rdparty/blobs/mainboard/amd/mandolin/mchp.bin" + default "3rdparty/blobs/mainboard/amd/mandolin/EC_mandolin.bin" if BOARD_AMD_MANDOLIN if !AMD_LPC_DEBUG_CARD choice MANDOLIN_LPC_IOMUX @@ -95,6 +103,6 @@ config VGA_BIOS_DGPU_ID config VGA_BIOS_DGPU_FILE string - default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" + default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN endif # BOARD_AMD_MANDOLIN diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc index de850b2c0a..1865e74dd9 100644 --- a/src/mainboard/amd/mandolin/Makefile.inc +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c -bootblock-y += early_gpio.c +bootblock-y += variants/$(VARIANT_DIR)/early_gpio.c -ramstage-y += gpio.c -ramstage-y += port_descriptors.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/port_descriptors.c ifneq ($(CONFIG_PICASSO_LPC_IOMUX),y) ramstage-y += emmc_gpio.c diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb deleted file mode 100644 index 495961feee..0000000000 --- a/src/mainboard/amd/mandolin/devicetree.cb +++ /dev/null @@ -1,85 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip soc/amd/picasso - register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" - - # Set FADT Configuration - register "fadt_pm_profile" = "PM_UNSPECIFIED" - register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" - register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ - ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_S4_RTC_WAKE | - ACPI_FADT_32BIT_TIMER | - ACPI_FADT_RESET_REGISTER | - ACPI_FADT_PCI_EXPRESS_WAKE | - ACPI_FADT_PLATFORM_CLOCK | - ACPI_FADT_S4_RTC_VALID | - ACPI_FADT_REMOTE_POWER_ON" - - register "sd_emmc_config" = "SD_EMMC_DISABLE" - - # eSPI Configuration - register "common_config.espi_config" = "{ - .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, - .generic_io_range[0] = { - .base = 0x662, - .size = 8, - }, - - .io_mode = ESPI_IO_MODE_SINGLE, - .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, - .crc_check_enable = 1, - .dedicated_alert_pin = 1, - .periph_ch_en = 0, - .vw_ch_en = 0, - .oob_ch_en = 0, - .flash_ch_en = 0, - }" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge - device pci 1.3 on end # Bridge to PCIe Ethernet chip - device pci 8.0 on end # Dummy Host Bridge - device pci 8.1 on # Bridge to Bus A - device pci 0.0 on end # Internal GPU - device pci 0.1 on end # Display HDA - device pci 0.2 on end # Crypto Coprocesor - device pci 0.3 on end # USB 3.1 - device pci 0.4 on end # USB 3.1 - device pci 0.5 on end # Audio - device pci 0.6 on end # HDA - device pci 0.7 on end # non-Sensor Fusion Hub device - end - device pci 8.2 on # Bridge to Bus B - device pci 0.0 on end # AHCI - device pci 0.1 off end # integrated Ethernet MAC - device pci 0.2 off end # integrated Ethernet MAC - end - device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 50 on end - device i2c 51 on end - end - end # SM - device pci 14.3 on # - D14F3 bridge - chip superio/smsc/sio1036 # optional debug card - end - end - device pci 14.6 off end # SDHCI - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end # domain -end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/early_gpio.c b/src/mainboard/amd/mandolin/early_gpio.c deleted file mode 100644 index b6dd0d6990..0000000000 --- a/src/mainboard/amd/mandolin/early_gpio.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "gpio.h" - -/* GPIO pins used by coreboot should be initialized in bootblock */ - -static const struct soc_amd_gpio gpio_set_stage_reset[] = { - /* not LLB */ - PAD_GPI(GPIO_12, PULL_UP), - /* not USB_OC5_L */ - PAD_GPI(GPIO_13, PULL_UP), - /* not USB_OC4_L */ - PAD_GPI(GPIO_14, PULL_UP), - /* not USB_OC1_L */ - PAD_GPI(GPIO_17, PULL_UP), - /* not USB_OC2_L */ - PAD_GPI(GPIO_18, PULL_UP), - /* SDIO eMMC power control */ - PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), - /* PCIe SSD power enable */ - PAD_GPO(GPIO_23, HIGH), - /* PCIe Reset to DP0, DP1, J2105, TP, FP */ - PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), - /* eSPI CS# */ - PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), - /* FANOUT0 */ - PAD_NF(GPIO_85, FANOUT0, PULL_NONE), - /* PC beep to codec */ - PAD_NF(GPIO_91, SPKR, PULL_NONE), -}; - -void mainboard_program_early_gpios(void) -{ - program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); -} diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c deleted file mode 100644 index 0d2e2faa47..0000000000 --- a/src/mainboard/amd/mandolin/gpio.c +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "gpio.h" - -/* - * As a rule of thumb, GPIO pins used by coreboot should be initialized at - * bootblock while GPIO pins used only by the OS should be initialized at - * ramstage. - */ -static const struct soc_amd_gpio gpio_set_stage_ram[] = { - /* SSD DEVSLP */ - PAD_NF(GPIO_5, DEVSLP0, PULL_NONE), - /* Defeature SATA Express DEVSLP, as some boards are reworked - * to tie this to GPIO23 to control power */ - PAD_GPI(GPIO_6, PULL_UP), - /* I2S SDIN */ - PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), - /* I2S LRCLK */ - PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), - /* Blink */ - PAD_NF(GPIO_11, BLINK, PULL_NONE), - /* APU_ALS_INT# */ - PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), - /* Finger print CS# */ - PAD_GPO(GPIO_31, HIGH), - /* NFC IRQ */ - PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), - /* Rear camera power enable */ - PAD_GPO(GPIO_89, HIGH), -}; - -void mainboard_program_gpios(void) -{ - program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); -} diff --git a/src/mainboard/amd/mandolin/mandolin.fmd b/src/mainboard/amd/mandolin/mandolin.fmd deleted file mode 100644 index 382c03066d..0000000000 --- a/src/mainboard/amd/mandolin/mandolin.fmd +++ /dev/null @@ -1,8 +0,0 @@ -FLASH@0xFF800000 0x800000 { - BIOS@0x0 { - EC@0x0 0x20000 - RW_MRC_CACHE@0x20000 0x10000 - FMAP 0x1000 - COREBOOT(CBFS) - } -} diff --git a/src/mainboard/amd/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/port_descriptors.c deleted file mode 100644 index d8969b2a66..0000000000 --- a/src/mainboard/amd/mandolin/port_descriptors.c +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -static const fsp_pcie_descriptor pco_pcie_descriptors[] = { - { /* MXM */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 15, - .device_number = 1, - .function_number = 1, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6 - }, - { /* SSD */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5 - }, - { /* WLAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0 - }, - { /* LAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1 - }, - { /* WWAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 2, - .end_lane = 2, - .device_number = 1, - .function_number = 4, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ2 - }, - { /* WIFI */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 3, - .end_lane = 3, - .gpio_group_id = 1, - .device_number = 1, - .function_number = 5, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ3 - }, - { /* SATA EXPRESS */ - .port_present = true, - .engine_type = SATA_ENGINE, - .start_lane = 6, - .end_lane = 7, - .gpio_group_id = 1, - .channel_type = SATA_CHANNEL_LONG, - } -}; - -static const fsp_pcie_descriptor dali_pcie_descriptors[] = { - { /* MXM */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 8, - .end_lane = 11, - .device_number = 1, - .function_number = 1, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ6 - }, - { /* SSD */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 0, - .end_lane = 1, - .device_number = 1, - .function_number = 7, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ5 - }, - { /* WLAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 4, - .end_lane = 4, - .device_number = 1, - .function_number = 2, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ0 - }, - { /* LAN */ - .port_present = true, - .engine_type = PCIE_ENGINE, - .start_lane = 5, - .end_lane = 5, - .device_number = 1, - .function_number = 3, - .link_aspm = ASPM_L1, - .link_aspm_L1_1 = true, - .link_aspm_L1_2 = true, - .turn_off_unused_lanes = true, - .clk_req = CLK_REQ1 - } -}; - -static const fsp_ddi_descriptor pco_ddi_descriptors[] = { - { /* DDI0 - DP */ - .connector_type = DP, - .aux_index = AUX1, - .hdp_index = HDP1 - }, - { /* DDI1 - eDP */ - .connector_type = EDP, - .aux_index = AUX2, - .hdp_index = HDP2 - }, - { /* DDI2 - DP */ - .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, - }, - { /* DDI3 - DP */ - .connector_type = DP, - .aux_index = AUX4, - .hdp_index = HDP4, - } -}; - -static const fsp_ddi_descriptor dali_ddi_descriptors[] = { - { /* DDI0 - DP */ - .connector_type = DP, - .aux_index = AUX1, - .hdp_index = HDP1 - }, - { /* DDI1 - eDP */ - .connector_type = EDP, - .aux_index = AUX2, - .hdp_index = HDP2 - }, - { /* DDI2 - DP */ - .connector_type = DP, - .aux_index = AUX3, - .hdp_index = HDP3, - } -}; - -void mainboard_get_pcie_ddi_descriptors( - const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, - const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) -{ - if (soc_is_reduced_io_sku()) { /* Dali */ - *pcie_descs = dali_pcie_descriptors; - *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); - *ddi_descs = dali_ddi_descriptors; - *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); - } else { /* Picasso and default */ - *pcie_descs = pco_pcie_descriptors; - *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); - *ddi_descs = pco_ddi_descriptors; - *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); - } -} diff --git a/src/mainboard/amd/mandolin/variants/mandolin/board.fmd b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd new file mode 100644 index 0000000000..382c03066d --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/mandolin/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF800000 0x800000 { + BIOS@0x0 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb new file mode 100644 index 0000000000..495961feee --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON" + + register "sd_emmc_config" = "SD_EMMC_DISABLE" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.3 on end # Bridge to PCIe Ethernet chip + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 on end # AHCI + device pci 0.1 off end # integrated Ethernet MAC + device pci 0.2 off end # integrated Ethernet MAC + end + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + device i2c 51 on end + end + end # SM + device pci 14.3 on # - D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c b/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c new file mode 100644 index 0000000000..678de59b2c --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/mandolin/early_gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC5_L */ + PAD_GPI(GPIO_13, PULL_UP), + /* not USB_OC4_L */ + PAD_GPI(GPIO_14, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe SSD power enable */ + PAD_GPO(GPIO_23, HIGH), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/mandolin/variants/mandolin/gpio.c b/src/mainboard/amd/mandolin/variants/mandolin/gpio.c new file mode 100644 index 0000000000..5270fd9610 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/mandolin/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* SSD DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0, PULL_NONE), + /* Defeature SATA Express DEVSLP, as some boards are reworked + * to tie this to GPIO23 to control power */ + PAD_GPI(GPIO_6, PULL_UP), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* Blink */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* Finger print CS# */ + PAD_GPO(GPIO_31, HIGH), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* Rear camera power enable */ + PAD_GPO(GPIO_89, HIGH), +}; + +void mainboard_program_gpios(void) +{ + program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); +} diff --git a/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c new file mode 100644 index 0000000000..d8969b2a66 --- /dev/null +++ b/src/mainboard/amd/mandolin/variants/mandolin/port_descriptors.c @@ -0,0 +1,208 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +static const fsp_pcie_descriptor pco_pcie_descriptors[] = { + { /* MXM */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 8, + .end_lane = 15, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6 + }, + { /* SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 2, + .end_lane = 2, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* WIFI */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 3, + .end_lane = 3, + .gpio_group_id = 1, + .device_number = 1, + .function_number = 5, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3 + }, + { /* SATA EXPRESS */ + .port_present = true, + .engine_type = SATA_ENGINE, + .start_lane = 6, + .end_lane = 7, + .gpio_group_id = 1, + .channel_type = SATA_CHANNEL_LONG, + } +}; + +static const fsp_pcie_descriptor dali_pcie_descriptors[] = { + { /* MXM */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 8, + .end_lane = 11, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6 + }, + { /* SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + } +}; + +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - eDP */ + .connector_type = EDP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { /* DDI3 - DP */ + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const fsp_ddi_descriptor dali_ddi_descriptors[] = { + { /* DDI0 - DP */ + .connector_type = DP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - eDP */ + .connector_type = EDP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + } +}; + +void mainboard_get_pcie_ddi_descriptors( + const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + if (soc_is_reduced_io_sku()) { /* Dali */ + *pcie_descs = dali_pcie_descriptors; + *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); + *ddi_descs = dali_ddi_descriptors; + *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); + } else { /* Picasso and default */ + *pcie_descs = pco_pcie_descriptors; + *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); + *ddi_descs = pco_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); + } +} -- cgit v1.2.3