From c045b099e460899a89c85727dda84a77e62fa072 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subratabanik@google.com>
Date: Mon, 3 Jan 2022 19:35:35 +0000
Subject: mb/starlabs/labtop: Replace leading whitespace with tab

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4d7324148ba182d0317b1f64e39f04a8a55fe79b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sean Rhodes <admin@starlabs.systems>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
---
 src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
index 2e001c6481..0b789146ae 100644
--- a/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
+++ b/src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
@@ -22,7 +22,7 @@ chip soc/intel/tigerlake
 	register "enable_c6dram"		= "1"
 	register "HeciEnabled"			= "1"
 	register "SaGv"				= "SaGv_Enabled"
-        register "TcssD3ColdDisable"		= "1"
+	register "TcssD3ColdDisable"		= "1"
 
 	# FSP Silicon
 	# Serial I/O
-- 
cgit v1.2.3