From c037695c195595d9ecc2112d0359b37cfe253345 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 16 Oct 2020 01:12:00 +0200 Subject: sec/intel/txt/ramstage.c: Do not init the heap on S3 resume It causes problems on Haswell: SINIT detects that the heap tables differ in size, and then issues a Class Code 9, Major Error Code 1 TXT reset. Change-Id: I26f3d291abc7b2263e0b115e94426ac6ec8e5c48 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46495 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/security/intel/txt/ramstage.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 2d56d1fd61..00e9ce72a2 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -407,7 +407,9 @@ static void lockdown_intel_txt(void *unused) write64((void *)TXT_MSEG_SIZE, 0); write64((void *)TXT_MSEG_BASE, 0); - txt_initialize_heap(); + /* Only initialize the heap on regular boots */ + if (!acpi_is_wakeup_s3()) + txt_initialize_heap(); if (CONFIG(INTEL_TXT_LOGGING)) txt_dump_regions(); -- cgit v1.2.3