From bfe0948f7d2f3df3c0f72e3e688527f0440c6591 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Fri, 7 Feb 2020 21:29:30 +0800 Subject: mb/google/drallion: Tuning WWAN power sequence Change GPP_C10 from pltrst to deep to meet the warmboot power sequence. BUG=b:146935222 TEST=measure WWAN power sequence is meet spec Signed-off-by: Eric Lai Change-Id: Ia1513ed38fbc1c99a10a5fa531a78cc92a3ebfc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38742 Tested-by: build bot (Jenkins) Reviewed-by: Mathew King --- src/mainboard/google/drallion/variants/drallion/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 1c864caff7..85de17346a 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -88,7 +88,7 @@ static const struct pad_config gpio_table[] = { /* SML0CLK */ PAD_NC(GPP_C3, NONE), /* SML0DATA */ PAD_NC(GPP_C4, NONE), /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), -/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, PLTRST), /* WWAN_FULL_PWR_EN */ +/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* WWAN_FULL_PWR_EN */ /* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART1_RXD */ PAD_NC(GPP_C12, NONE), /* UART1_TXD */ PAD_NC(GPP_C13, NONE), -- cgit v1.2.3