From be0722ac9145ac0203aca26165cbc9ee46b2b1b7 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Fri, 19 Nov 2021 13:18:22 +0900 Subject: mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8 which is calibrated value for the board. BUG=b:207046230 BRANCH=dedede TEST=build firmware to UPD and Acoustic noise test Signed-off-by: Seunghwan Kim Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/dedede/variants/bugzzy/overridetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb index e1318a8e46..de1e46d0df 100644 --- a/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb +++ b/src/mainboard/google/dedede/variants/bugzzy/overridetree.cb @@ -2,6 +2,12 @@ chip soc/intel/jasperlake # MIPI display panel register "DdiPortAConfig" = "2" # DdiPortMipiDsi + # Enable Acoustic noise mitigation and set slew rate to 1/8 + # Rest of the parameters are 0 by default. + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SlewRateFastBy8" + register "FastPkgCRampDisable" = "1" + # Disable PCIe Root Port 8 (index 7) register "PcieRpEnable[7]" = "0" # Disable PCIe Clock Source 4 (index 3) -- cgit v1.2.3