From bd529e2e200a8fbfd455dd62be0494a2b727b9a5 Mon Sep 17 00:00:00 2001 From: Usha P Date: Thu, 10 Mar 2022 14:36:57 +0530 Subject: mb/google/nissa/var/nivviks: Add TcssAuxori for nivviks Enable SBU orientation handling by SoC for both USBC port0 and USBC port1. Nivviks USBC port0 do not have retimer, USBC port1 has redriver, but that do not flip the data lines. Hence we need to set bits for both the USBC ports. BRANCH:None TEST=emerge-nissa coreboot chromeos-bootimage. Flash the image on nivviks board and verified USBC display is working on both the ports in normal and inverted connections. Signed-off-by: Usha P Change-Id: I219de6092ac9a9c773adbaa99f5a7d6196a2c937 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62731 Reviewed-by: Rizwan Qureshi Reviewed-by: Reka Norman Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) --- src/mainboard/google/brya/variants/nivviks/overridetree.cb | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/brya/variants/nivviks/overridetree.cb b/src/mainboard/google/brya/variants/nivviks/overridetree.cb index c2eac2d97a..d423ffb5ce 100644 --- a/src/mainboard/google/brya/variants/nivviks/overridetree.cb +++ b/src/mainboard/google/brya/variants/nivviks/overridetree.cb @@ -9,6 +9,15 @@ end chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "TcssAuxOri" = "5" + register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" -- cgit v1.2.3