From bc979cc904db24dcc78779a11940e0ac2be303c0 Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Thu, 28 Nov 2019 14:18:12 +0100 Subject: pcengines/apu1: Switch away from ROMCC_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=boot PC Engines apu1 with C bootblock patch and launch Debian with Linux kernel 4.14.50 Signed-off-by: Michał Żygowski Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu1/Kconfig | 1 - src/mainboard/pcengines/apu1/Makefile.inc | 2 ++ src/mainboard/pcengines/apu1/bootblock.c | 25 +++++++++++++++++++++++++ src/mainboard/pcengines/apu1/romstage.c | 2 -- 4 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 src/mainboard/pcengines/apu1/bootblock.c (limited to 'src') diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 168423632b..3396845559 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -18,7 +18,6 @@ if BOARD_PCENGINES_APU1 config BOARD_SPECIFIC_OPTIONS def_bool y - select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/pcengines/apu1/Makefile.inc b/src/mainboard/pcengines/apu1/Makefile.inc index 543ac97723..3aa3bbe67c 100644 --- a/src/mainboard/pcengines/apu1/Makefile.inc +++ b/src/mainboard/pcengines/apu1/Makefile.inc @@ -21,6 +21,8 @@ pci$(stripped_ahcibios_id).rom-file := $(call strip_quotes,$(CONFIG_AHCI_BIOS_FI pci$(stripped_ahcibios_id).rom-type := optionrom endif +bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c new file mode 100644 index 0000000000..2d34cba3bf --- /dev/null +++ b/src/mainboard/pcengines/apu1/bootblock.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include + +#define SIO_PORT 0x2e +#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1) + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c index da0e0d3d5e..20a6318a46 100644 --- a/src/mainboard/pcengines/apu1/romstage.c +++ b/src/mainboard/pcengines/apu1/romstage.c @@ -61,7 +61,5 @@ static void early_lpc_init(void) void board_BeforeAgesa(struct sysinfo *cb) { - sb_Poweron_Init(); early_lpc_init(); - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -- cgit v1.2.3