From bc58a878cd0ae34ca9ebfc66bfc8ca440e58a0eb Mon Sep 17 00:00:00 2001 From: david Date: Mon, 28 Dec 2015 20:28:58 +0800 Subject: google/lars: Enable SaGv feature This change enables SaGv feature for skylake platform. As a result of this patch the skylake platform will train memory at both low & high frequency points. This will be used to dynamically scale the work point (voltage/frequencies). The value "3" here means enable. Following is the table for same. 0=Disabled (SaGv disabled) 1=FixedLow (Fixed to low frequency) 2=FixedHigh (Fixed to High frequency) 3=Enabled( SaGv Enabled.Dynamically changes) BRANCH=None BUG=chrome-os-partner:48534 TEST=Build and boot lars Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d Signed-off-by: Patrick Georgi Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1 Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557 Original-Signed-off-by: David Wu Original-Reviewed-on: https://chromium-review.googlesource.com/320022 Original-Commit-Ready: David Wu Original-Tested-by: David Wu Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Subrata Banik Original-Reviewed-by: Haridhar Kalvala Reviewed-on: https://review.coreboot.org/13002 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/google/lars/devicetree.cb | 1 + 1 file changed, 1 insertion(+) (limited to 'src') diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index ed47820f39..689babb5a5 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -30,6 +30,7 @@ chip soc/intel/skylake register "SkipExtGfxScan" = "1" register "Device4Enable" = "1" register "HeciEnabled" = "0" + register "SaGv" = "3" register "FspSkipMpInit" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch -- cgit v1.2.3