From bbf5de55caebd6814db129e484aeb158fc7eafd5 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 23 Mar 2022 22:41:05 +0100 Subject: sb/amd/hudson/spi.c: Use C over CPP conditional Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/63056 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Felix Held --- src/southbridge/amd/agesa/hudson/spi.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) (limited to 'src') diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index b2f9ff2f72..986f094a77 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -97,15 +97,15 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - spi_write(0x1E, 5); - spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ - spi_write(0x1E, 6); - spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ -#else - u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; - spi_write(SPI_REG_CNTRL01, readwrite); -#endif + if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) { + spi_write(0x1E, 5); + spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + spi_write(0x1E, 6); + spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ + } else { + u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; + spi_write(SPI_REG_CNTRL01, readwrite); + } spi_write(SPI_REG_OPCODE, cmd); reset_internal_fifo_pointer(); -- cgit v1.2.3