From bb7e2befa3da30f38858af08db7f9f22e967054d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Thu, 21 Nov 2024 17:00:49 +0530 Subject: mb/google/fatcat: Move CSE sync at payload The CSE sync in the payload would allow CrOS devices to render the user notification when updating. Currently, CrOS devices typically take 8-20 seconds to do a CSE sync. BUG=b:380220737 TEST=Able to build and boot google/fatcat. Change-Id: I8f1dd2e153ed0f1e671699002cf34a58d758ce2f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/85233 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 1851cdee4a..c693bd2f61 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -31,9 +31,8 @@ config BOARD_GOOGLE_FATCAT_COMMON select MAINBOARD_HAS_TPM2 select MB_COMPRESS_RAMSTAGE_LZ4 select PMC_IPC_ACPI_INTERFACE - select SOC_INTEL_CSE_LITE_SKU - select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 - select SOC_INTEL_CSE_SEND_EOP_ASYNC + select SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD + select SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD select SOC_INTEL_PANTHERLAKE_U_H select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION -- cgit v1.2.3