From bb1ecc56624fc57b030cbbada2add6cc3bfd004e Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 11 Apr 2022 14:57:58 -0700 Subject: intel/common/block: rename dmi folder to gpmr as starting gpmr migration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As a start of GPMR(General Purpose Memory Range) driver migration, 1. rename dmi folder to gpmr folder 2. rename dmi.c to gpmr.c TEST=build Signed-off-by: Wonkyu Kim Change-Id: I4d57f4b8bd06e0cf6c9afa4baf4a7bed64ecb56b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63170 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Subrata Banik Reviewed-by: Michael Niewöhner --- src/soc/intel/common/block/dmi/Kconfig | 5 -- src/soc/intel/common/block/dmi/Makefile.inc | 7 --- src/soc/intel/common/block/dmi/dmi.c | 81 ---------------------------- src/soc/intel/common/block/gpmr/Kconfig | 5 ++ src/soc/intel/common/block/gpmr/Makefile.inc | 7 +++ src/soc/intel/common/block/gpmr/gpmr.c | 81 ++++++++++++++++++++++++++++ 6 files changed, 93 insertions(+), 93 deletions(-) delete mode 100644 src/soc/intel/common/block/dmi/Kconfig delete mode 100644 src/soc/intel/common/block/dmi/Makefile.inc delete mode 100644 src/soc/intel/common/block/dmi/dmi.c create mode 100644 src/soc/intel/common/block/gpmr/Kconfig create mode 100644 src/soc/intel/common/block/gpmr/Makefile.inc create mode 100644 src/soc/intel/common/block/gpmr/gpmr.c (limited to 'src') diff --git a/src/soc/intel/common/block/dmi/Kconfig b/src/soc/intel/common/block/dmi/Kconfig deleted file mode 100644 index 2cc4646312..0000000000 --- a/src/soc/intel/common/block/dmi/Kconfig +++ /dev/null @@ -1,5 +0,0 @@ -config SOC_INTEL_COMMON_BLOCK_DMI - bool - select SOC_INTEL_COMMON_BLOCK_PCR - help - Intel Processor common DMI support diff --git a/src/soc/intel/common/block/dmi/Makefile.inc b/src/soc/intel/common/block/dmi/Makefile.inc deleted file mode 100644 index 7d013c96bc..0000000000 --- a/src/soc/intel/common/block/dmi/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) - -bootblock-y += dmi.c -romstage-y += dmi.c -ramstage-y += dmi.c - -endif diff --git a/src/soc/intel/common/block/dmi/dmi.c b/src/soc/intel/common/block/dmi/dmi.c deleted file mode 100644 index 1a3a6023d6..0000000000 --- a/src/soc/intel/common/block/dmi/dmi.c +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -#define MAX_GPMR_REGS 3 - -#define GPMR_OFFSET(x) (0x277c + (x) * 8) -#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 -#define DMI_PCR_GPMR_BASE_SHIFT 16 -#define DMI_PCR_GPMR_BASE_MASK 0xffff - -#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) -#define DMI_PCR_GPMR_EN BIT(31) - -/* GPMR Register read given offset */ -static uint32_t gpmr_read32(uint16_t offset) -{ - return pcr_read32(PID_DMI, offset); -} - -/* GPMR Register write given offset and val */ -static void gpmr_write32(uint16_t offset, uint32_t val) -{ - return pcr_write32(PID_DMI, offset, val); -} - -/* Check for available free gpmr */ -static int get_available_gpmr(void) -{ - int i; - uint32_t val; - - for (i = 0; i < MAX_GPMR_REGS; i++) { - val = gpmr_read32(GPMR_DID_OFFSET(i)); - if (!(val & DMI_PCR_GPMR_EN)) - return i; - } - printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); - return CB_ERR; -} - -/* Configure GPMR for the given base and size of extended BIOS Region */ -enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) -{ - int gpmr_num; - uint32_t limit; - - if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { - printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); - return CB_ERR; - } - - limit = base + (size - 1); - - if (limit < base) { - printk(BIOS_ERR, "Invalid limit: limit cannot be less than base!\n"); - return CB_ERR; - } - - if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { - printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); - return CB_ERR; - } - - /* Get available free GPMR */ - gpmr_num = get_available_gpmr(); - if (gpmr_num == CB_ERR) - return CB_ERR; - - /* Program Range for the given decode window */ - gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | - ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); - - /* Program source decode enable bit and the Destination ID */ - gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); - - return CB_SUCCESS; -} diff --git a/src/soc/intel/common/block/gpmr/Kconfig b/src/soc/intel/common/block/gpmr/Kconfig new file mode 100644 index 0000000000..2cc4646312 --- /dev/null +++ b/src/soc/intel/common/block/gpmr/Kconfig @@ -0,0 +1,5 @@ +config SOC_INTEL_COMMON_BLOCK_DMI + bool + select SOC_INTEL_COMMON_BLOCK_PCR + help + Intel Processor common DMI support diff --git a/src/soc/intel/common/block/gpmr/Makefile.inc b/src/soc/intel/common/block/gpmr/Makefile.inc new file mode 100644 index 0000000000..0abf61fda5 --- /dev/null +++ b/src/soc/intel/common/block/gpmr/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_DMI), y) + +bootblock-y += gpmr.c +romstage-y += gpmr.c +ramstage-y += gpmr.c + +endif diff --git a/src/soc/intel/common/block/gpmr/gpmr.c b/src/soc/intel/common/block/gpmr/gpmr.c new file mode 100644 index 0000000000..1a3a6023d6 --- /dev/null +++ b/src/soc/intel/common/block/gpmr/gpmr.c @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define MAX_GPMR_REGS 3 + +#define GPMR_OFFSET(x) (0x277c + (x) * 8) +#define DMI_PCR_GPMR_LIMIT_MASK 0xffff0000 +#define DMI_PCR_GPMR_BASE_SHIFT 16 +#define DMI_PCR_GPMR_BASE_MASK 0xffff + +#define GPMR_DID_OFFSET(x) (0x2780 + (x) * 8) +#define DMI_PCR_GPMR_EN BIT(31) + +/* GPMR Register read given offset */ +static uint32_t gpmr_read32(uint16_t offset) +{ + return pcr_read32(PID_DMI, offset); +} + +/* GPMR Register write given offset and val */ +static void gpmr_write32(uint16_t offset, uint32_t val) +{ + return pcr_write32(PID_DMI, offset, val); +} + +/* Check for available free gpmr */ +static int get_available_gpmr(void) +{ + int i; + uint32_t val; + + for (i = 0; i < MAX_GPMR_REGS; i++) { + val = gpmr_read32(GPMR_DID_OFFSET(i)); + if (!(val & DMI_PCR_GPMR_EN)) + return i; + } + printk(BIOS_ERR, "%s: No available free gpmr found\n", __func__); + return CB_ERR; +} + +/* Configure GPMR for the given base and size of extended BIOS Region */ +enum cb_err dmi_enable_gpmr(uint32_t base, uint32_t size, uint32_t dest_id) +{ + int gpmr_num; + uint32_t limit; + + if (base & ~(DMI_PCR_GPMR_BASE_MASK << DMI_PCR_GPMR_BASE_SHIFT)) { + printk(BIOS_ERR, "base is not 64-KiB aligned!\n"); + return CB_ERR; + } + + limit = base + (size - 1); + + if (limit < base) { + printk(BIOS_ERR, "Invalid limit: limit cannot be less than base!\n"); + return CB_ERR; + } + + if ((limit & ~DMI_PCR_GPMR_LIMIT_MASK) != 0xffff) { + printk(BIOS_ERR, "limit does not end on a 64-KiB boundary!\n"); + return CB_ERR; + } + + /* Get available free GPMR */ + gpmr_num = get_available_gpmr(); + if (gpmr_num == CB_ERR) + return CB_ERR; + + /* Program Range for the given decode window */ + gpmr_write32(GPMR_OFFSET(gpmr_num), (limit & DMI_PCR_GPMR_LIMIT_MASK) | + ((base >> DMI_PCR_GPMR_BASE_SHIFT) & DMI_PCR_GPMR_BASE_MASK)); + + /* Program source decode enable bit and the Destination ID */ + gpmr_write32(GPMR_DID_OFFSET(gpmr_num), dest_id | DMI_PCR_GPMR_EN); + + return CB_SUCCESS; +} -- cgit v1.2.3