From ba817d0931eb9bbf23d6c09f56f9ea2ba22fdad6 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Wed, 6 Apr 2016 22:07:58 -0500 Subject: nb/amd/mct_ddr3: Reenable sync flood after ECC init The sync flood reset fix in Change-Id: I62d897010a8120aa14b4cb8d096bc4f2edc5f248 and related changes have made it possible to move the sync flood enable statements back into romstage. Change-Id: I5a3a4f1621e3048f9dfc159709410be9de6ebece Signed-off-by: Timothy Pearson Reviewed-on: https://review.coreboot.org/14270 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Martin Roth --- src/northbridge/amd/amdfam10/misc_control.c | 8 -------- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 9 +++++++++ 2 files changed, 9 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index eee5c465fb..775af66b9d 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -186,14 +186,6 @@ static void misc_control_init(struct device *dev) /* Clear MC4 error status */ pci_write_config32(dev, 0x48, 0x0); pci_write_config32(dev, 0x4c, 0x0); - - if (mem_info->dct_stat[node].mca_config_backed_up) { - dword = pci_read_config32(dev, 0x44); - dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; - dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; - dword |= (mem_info->dct_stat[node].sync_flood_on_uc_dram_ecc_err & 0x1) << 2; - pci_write_config32(dev, 0x44, dword); - } } } #endif diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 65de0f8c6a..203d11273d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -264,6 +264,15 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + + /* Restore MCA settings */ + if (pDCTstat->mca_config_backed_up) { + val = pci_read_config32(pDCTstat->dev_nbmisc, 0x44); + val |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; + val |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; + val |= (pDCTstat->sync_flood_on_uc_dram_ecc_err & 0x1) << 2; + pci_write_config32(pDCTstat->dev_nbmisc, 0x44, val); + } } } } -- cgit v1.2.3