From b8fad3d02986222fa162d455eca2ffe807b6a15a Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Tue, 27 Aug 2013 15:48:32 -0700 Subject: arm: libpayload: Add cache coherent DMA memory definition and management This patch adds a mechanism to set aside a region of cache-coherent (i.e. usually uncached) virtual memory, which can be used to communicate with DMA devices without automatic cache snooping (common on ARM) without the need of explicit flush/invalidation instructions in the driver code. This works by setting aside said region in the (board-specific) page table setup, as exemplary done in this patch for the Snow and Pit boards. It uses a new mechanism for adding board-specific Coreboot table entries to describe this region in an entry with the LB_DMA tag. Libpayload's memory allocator is enhanced to be able to operate on distinct types/regions of memory. It provides dma_malloc() and dma_memalign() functions for use in drivers, which by default just operate on the same heap as their traditional counterparts. However, if the Coreboot table parsing code finds a CB_DMA section, further requests through the dma_xxx() functions will return memory from the region described therein instead. Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186 Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/167155 (cherry picked from commit d142ccdcd902a9d6ab4d495fbe6cbe85c61a5f01) Signed-off-by: Isaac Christensen Reviewed-on: http://review.coreboot.org/6622 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/include/boot/coreboot_tables.h | 6 ++++++ src/lib/coreboot_table.c | 7 ++++++- src/mainboard/google/pit/mainboard.c | 16 ++++++++++++++++ src/mainboard/google/snow/mainboard.c | 16 ++++++++++++++++ 4 files changed, 44 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index 3c569a132d..db3c508285 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -218,6 +218,7 @@ struct lb_gpios { #define LB_TAG_VDAT 0x0015 #define LB_TAG_VBNV 0x0019 #define LB_TAB_VBOOT_HANDOFF 0x0020 +#define LB_TAB_DMA 0x0022 struct lb_range { uint32_t tag; uint32_t size; @@ -332,4 +333,9 @@ void uart_fill_lb(void *data); void lb_add_serial(struct lb_serial *serial, void *data); void lb_add_console(uint16_t consoletype, void *data); +/* Define this in mainboard.c to add board-specific table entries. */ +void lb_board(struct lb_header *header); + +struct lb_record *lb_new_record(struct lb_header *header); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index f0ae6c5bc0..9f9c453a5b 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -77,7 +77,7 @@ static struct lb_record *lb_last_record(struct lb_header *header) return rec; } -static struct lb_record *lb_new_record(struct lb_header *header) +struct lb_record *lb_new_record(struct lb_header *header) { struct lb_record *rec; rec = lb_last_record(header); @@ -298,6 +298,8 @@ static void lb_strings(struct lb_header *header) } +void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ } + static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { struct lb_record *rec; @@ -425,6 +427,9 @@ unsigned long write_coreboot_table( #endif add_cbmem_pointers(head); + /* Add board-specific table entries, if any. */ + lb_board(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 77c54a189f..467b9d04e9 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -45,6 +45,10 @@ #define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB +/* Arbitrary range of DMA memory for depthcharge's drivers */ +#define DMA_START (0x77300000) +#define DMA_SIZE (0x00100000) + static struct edid edid = { .ha = 1366, .va = 768, @@ -452,6 +456,7 @@ static void mainboard_enable(device_t dev) /* set up caching for the DRAM */ mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); tlb_invalidate_all(); /* this is going to move, but we must have it now and we're @@ -472,3 +477,14 @@ struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM Chromebook", .enable_dev = mainboard_enable, }; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (intptr_t)DMA_START; + dma->range_size = DMA_SIZE; +} diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c index d209a762fc..dfaf81d537 100644 --- a/src/mainboard/google/snow/mainboard.c +++ b/src/mainboard/google/snow/mainboard.c @@ -46,6 +46,10 @@ #define DRAM_SIZE CONFIG_DRAM_SIZE_MB #define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ +/* Arbitrary range of DMA memory for depthcharge's drivers */ +#define DMA_START (0x77300000) +#define DMA_SIZE (0x00100000) + static struct edid edid = { .ha = 1366, .va = 768, @@ -320,6 +324,7 @@ static void mainboard_enable(device_t dev) mmu_init(); mmu_config_range(0, DRAM_START, DCACHE_OFF); mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF); mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); dcache_invalidate_all(); dcache_mmu_enable(); @@ -342,3 +347,14 @@ struct chip_operations mainboard_ops = { .name = "Samsung/Google ARM Chromebook", .enable_dev = mainboard_enable, }; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = (intptr_t)DMA_START; + dma->range_size = DMA_SIZE; +} -- cgit v1.2.3