From b75bcc978af50dc409b5356abd33b064029480bb Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Sun, 22 Mar 2020 22:16:03 -0700 Subject: mb/ocp/tiogapass: Properly configure early serial output Tioga Pass comes with AST2500 BMC which offers SuperIO functionality. However we currently do not configure/enable SuperIO chip. As a result system boots pretty silently on cold boot. Then FSP configures SuperIO and resets the system so on next boot serial console does work. This makes debugging difficult because pre-FSP output is invisible. This patch enables bootblock to properly configure desired BMC SuperIO port so early serial output is visible. TEST=do a cold boot on OCP Tioga Pass, observe bootblock output starting from bootblock. Change-Id: Iff8e6a862858d733f529bb9b8c65e22e5ec6b521 Signed-off-by: Andrey Petrov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39782 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/mainboard/ocp/tiogapass/Kconfig | 1 + src/mainboard/ocp/tiogapass/Makefile.inc | 1 + src/mainboard/ocp/tiogapass/bootblock.c | 59 ++++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) create mode 100644 src/mainboard/ocp/tiogapass/bootblock.c (limited to 'src') diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig index 1d501e6db0..f9b5e7f48a 100644 --- a/src/mainboard/ocp/tiogapass/Kconfig +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_USES_FSP2_0 select IPMI_KCS select SOC_INTEL_SKYLAKE_SP + select SUPERIO_ASPEED_AST2400 config MAINBOARD_DIR string diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc index 7a0a43fb8f..27370fd57a 100644 --- a/src/mainboard/ocp/tiogapass/Makefile.inc +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -13,6 +13,7 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.c ramstage-y += ramstage.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000000..d9a86e99f0 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* these are defined in intelblocks/lpc_lib.h but we can't use them yet */ +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 + +static void enable_espi_lpc_io_windows(void) +{ + /* + * Set up decoding windows on PCH over PCR. The CPUs use two of AST2500 SIO ports, + * one is connected to debug header (SUART1) and another is used as SOL (SUART2). + * For that end it is wired into BMC virtual port. + */ + + /* Open IO windows: 0x3f8 for com1 and 02e8 for com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOD, (0 << 0) | (1 << 4)); + /* LPC I/O enable: com1 and com2 */ + pcr_or32(PID_DMI, PCR_DMI_LPCIOE, (1 << 0) | (1 << 1)); + + /* Enable com1 (0x3f8), com2 (02f8) and superio (0x2e) */ + pci_mmio_write_config32(PCH_DEV_LPC, 0x80, + (1<<28) | (1<<16) | (1<<17) | (0 << 0) | (1 << 4)); +} + +static uint8_t com_to_ast_sio(uint8_t com) +{ + switch (com) { + case 0: + return AST2400_SUART1; + case 1: + return AST2400_SUART2; + case 2: + return AST2400_SUART3; + case 4: + return AST2400_SUART4; + default: + return AST2400_SUART1; + } +} + +void bootblock_mainboard_early_init(void) +{ + /* Open IO windows */ + enable_espi_lpc_io_windows(); + + /* Configure appropriate physical port of SuperIO chip off BMC */ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, com_to_ast_sio(CONFIG_UART_FOR_CONSOLE)); + aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} -- cgit v1.2.3