From b6a4476f342afa0b65f15b2f225d2e1dc3b3c776 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Thu, 22 Apr 2021 17:03:56 -0600 Subject: mb/google/guybrush: Enable S0i3 BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Mathew King Reviewed-by: Marshall Dawson --- src/mainboard/google/guybrush/variants/baseboard/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 84bdfcf206..305dfbfc6f 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -38,6 +38,9 @@ chip soc/amd/cezanne .vw_irq_polarity = ESPI_VW_IRQ_LEVEL_HIGH(1), }" + # Enable S0i3 support + register "s0ix_enable" = "1" + register "i2c_scl_reset" = "GPIO_I2C0_SCL | GPIO_I2C1_SCL | GPIO_I2C2_SCL | GPIO_I2C3_SCL" -- cgit v1.2.3