From b4a45dcf9d442b311dec7396a55be917713a0d15 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 26 Jul 2013 08:53:59 +0300 Subject: intel PCI ops: Remove explicit PCI MMCONF access MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17545 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/soc/intel/broadwell/pcie.c | 2 +- src/soc/intel/skylake/pcie.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_bd82x6x/azalia.c | 18 +++++++++--------- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 7 ------- src/southbridge/intel/ibexpeak/me.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- 11 files changed, 18 insertions(+), 25 deletions(-) (limited to 'src') diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 1c9b50cceb..355e17abfc 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -673,7 +673,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c index 719abf33e3..d3eecff585 100644 --- a/src/soc/intel/skylake/pcie.c +++ b/src/soc/intel/skylake/pcie.c @@ -75,7 +75,7 @@ static void pch_pcie_init(struct device *dev) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for the SOC */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 23915c3a80..0e5187c08f 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -33,7 +33,7 @@ #include #ifdef __SMM__ -#include +#include #else # include # include diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 220a176739..94cec3e701 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -33,7 +33,7 @@ #include #ifdef __SMM__ -#include +#include #else # include # include diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 71ebb6e0e6..4cef988ef1 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -28,7 +28,7 @@ #include "nvs.h" #include -#include +#include #include #include #include diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index c58f402195..093017eda2 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,7 +35,7 @@ #ifdef __SMM__ -#include +#include #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index b64d923125..b8cdd9710c 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -245,28 +245,28 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 25 for server reg32 |= RCBA32(0x2030) & 0xfe; - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); - reg16 = pci_mmio_read_config16(dev, 0x78); + reg16 = pci_read_config16(dev, 0x78); reg16 &= ~(1 << 11); - pci_mmio_write_config16(dev, 0x78, reg16); + pci_write_config16(dev, 0x78, reg16); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= ~0xfe; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); } // Enable HDMI codec: diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index acdb0729c7..8026698721 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -28,7 +28,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set); #ifdef __SMM__ -#include +#include #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index c6425dba51..2c21ea7757 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -212,7 +212,6 @@ static u32 reset_tco_status(void) return reg32; } - static void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -232,12 +231,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e2eb41c936..da6bfa81f5 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -32,7 +32,7 @@ #include #ifdef __SMM__ -#include +#include #else # include # include diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index c3db159484..ec91bdf3fc 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -33,7 +33,7 @@ */ #include "northbridge/intel/nehalem/nehalem.h" #include -#include +#include /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value -- cgit v1.2.3