From b3fa6a03a895ee43e9679d5c6608e98d1eec6e67 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Thu, 27 Feb 2020 15:54:56 -0800 Subject: soc/intel/tigerlake: configure ethernet Configure ethernet based on board config BUG=none BRANCH=none TEST= build TGLRVP and check ethernet is disabled based on devicetree Signed-off-by: Wonkyu Kim Change-Id: I3286f5fefc962a5e55b5554982271ed6b885f7d8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39153 Reviewed-by: Srinidhi N Kaushik Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/tigerlake/fsp_params_tgl.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c index d22cde021c..fbc9f23083 100644 --- a/src/soc/intel/tigerlake/fsp_params_tgl.c +++ b/src/soc/intel/tigerlake/fsp_params_tgl.c @@ -135,6 +135,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* LAN */ + dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6); + if (!dev) + params->PchLanEnable = 0; + else + params->PchLanEnable = dev->enabled; + /* Legacy 8254 timer support */ params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER; -- cgit v1.2.3