From b3aaa63e8f99bb9ae32d08136f59a72d3b97de10 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 11 Nov 2020 11:26:52 +0100 Subject: soc/intel/denverton_ns: Hook up SMMSTORE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested on Intel Harcuvar CRB, SMMSTORE is now working. Change-Id: I996c7bf3b510a8f0a9d1bb7d945ce777b646448e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47450 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Nico Huber Reviewed-by: Michael Niewöhner --- src/soc/intel/denverton_ns/smihandler.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) (limited to 'src') diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 5eecba7a31..cae8b9b5f8 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -197,6 +198,26 @@ static void finalize(void) fast_spi_init(); } +static void southbridge_smi_store(void) +{ + u8 sub_command, ret; + em64t100_smm_state_save_area_t *io_smi = + smi_apmc_find_state_save(APM_CNT_SMMSTORE); + uint32_t reg_ebx; + + if (!io_smi) + return; + /* Command and return value in EAX */ + sub_command = (io_smi->rax >> 8) & 0xff; + + /* Parameter buffer in EBX */ + reg_ebx = io_smi->rbx; + + /* drivers/smmstore/smi.c */ + ret = smmstore_exec(sub_command, (void *)reg_ebx); + io_smi->rax = ret; +} + static void southbridge_smi_apmc(void) { uint8_t reg8; @@ -245,6 +266,10 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + southbridge_smi_store(); + break; } mainboard_smi_apmc(reg8); -- cgit v1.2.3