From b37d01d3093d45528b1447d792d88f85607595ca Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 21 Jul 2016 21:08:28 +0300 Subject: intel/haswell: Add asmlinkage for romstage_after_car() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ib3c973d2e89d4c25c3bf1e52662fbfcb4b1e4355 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15789 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/cpu/intel/haswell/haswell.h | 2 +- src/cpu/intel/haswell/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8298fb1699..41cd5ba684 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -183,7 +183,7 @@ void romstage_common(const struct romstage_params *params); void * asmlinkage romstage_main(unsigned long bist); /* romstage_after_car() is the C function called after cache-as-ram has * been torn down. It is responsible for loading the ramstage. */ -void romstage_after_car(void); +void asmlinkage romstage_after_car(void); #endif #ifdef __SMM__ diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9154316d91..8b15ed546e 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -259,7 +259,7 @@ void romstage_common(const struct romstage_params *params) } } -void romstage_after_car(void) +void asmlinkage romstage_after_car(void) { /* Load the ramstage. */ run_ramstage(); -- cgit v1.2.3