From b3621f811d226c322fc6b21b583270c6b40e7e4c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 4 Dec 2020 19:51:17 +0200 Subject: soc/amd: Remove Kconfig BOOTBLOCK_ADDR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due the location of X86_RESET_VECTOR, the anchor point for linking the bootblock is at the end, which equals ROMSTAGE_ADDR. Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Felix Held --- src/soc/amd/cezanne/Kconfig | 6 ------ src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld | 15 +++++++++------ src/soc/amd/picasso/Kconfig | 6 ------ src/soc/amd/picasso/root_complex.c | 6 +++--- 4 files changed, 12 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index d2badc9ee5..fe248c6097 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -47,12 +47,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated -config BOOTBLOCK_ADDR - hex - default 0x2030000 - help - Sets the address in DRAM where bootblock should be loaded. - config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index dae69d030f..f702b4b201 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -10,6 +10,9 @@ #define PSP_SHAREDMEM_DRAM_START(addr) SYMBOL(psp_sharedmem_dram, addr) #define PSP_SHAREDMEM_DRAM_END(addr) SYMBOL(epsp_sharedmem_dram, addr) +BOOTBLOCK_END = CONFIG_ROMSTAGE_ADDR; +BOOTBLOCK_ADDR = BOOTBLOCK_END - CONFIG_C_ENV_BOOTBLOCK_SIZE; + /* * * +--------------------------------+ @@ -31,11 +34,11 @@ * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * +--------------------------------+ * | FMAP cache (FMAP_SIZE) | @@ -84,8 +87,8 @@ SECTIONS #if CONFIG(VBOOT) PSP_SHAREDMEM_DRAM_END(CONFIG_PSP_SHAREDMEM_BASE + CONFIG_PSP_SHAREDMEM_SIZE) #endif - _ = ASSERT(CONFIG_BOOTBLOCK_ADDR == ((CONFIG_BOOTBLOCK_ADDR + 0xFFFF) & 0xFFFF0000), "Bootblock must be 16 bit aligned"); - BOOTBLOCK(CONFIG_BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) + _ = ASSERT(BOOTBLOCK_END == ((BOOTBLOCK_END + 0xFFFF) & 0xFFFF0000), "Bootblock end must be 16 bit aligned"); + BOOTBLOCK(BOOTBLOCK_ADDR, CONFIG_C_ENV_BOOTBLOCK_SIZE) ROMSTAGE(CONFIG_ROMSTAGE_ADDR, CONFIG_ROMSTAGE_SIZE) REGION(fspm, CONFIG_FSP_M_ADDR, CONFIG_FSP_M_SIZE, 1) #if CONFIG(VBOOT_SEPARATE_VERSTAGE) @@ -107,7 +110,7 @@ SECTIONS { _TOO_LOW = _X86_RESET_VECTOR - 0xfff0; _bogus = ASSERT(_start16bit >= _TOO_LOW, "_start16bit too low. Please report."); - . = CONFIG_BOOTBLOCK_ADDR + CONFIG_C_ENV_BOOTBLOCK_SIZE - 0x10; + . = BOOTBLOCK_END - 0x10; _X86_RESET_VECTOR = .; .reset . : { *(.reset); diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index fcb7ddbed5..bd9964bd8f 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -120,12 +120,6 @@ config PRERAM_CBMEM_CONSOLE_SIZE help Increase this value if preram cbmem console is getting truncated -config BOOTBLOCK_ADDR - hex - default 0x2030000 - help - Sets the address in DRAM where bootblock should be loaded. - config C_ENV_BOOTBLOCK_SIZE hex default 0x10000 diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 259419cb97..7ca44b02a7 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -77,11 +77,11 @@ struct dptc_input { * +--------------------------------+ FSP_M_ADDR * | romstage | * | (ROMSTAGE_SIZE) | - * +--------------------------------+ ROMSTAGE_ADDR - * | | X86_RESET_VECTOR = BOOTBLOCK_ADDR + C_ENV_BOOTBLOCK_SIZE - 0x10 + * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END + * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 * | bootblock | * | (C_ENV_BOOTBLOCK_SIZE) | - * +--------------------------------+ BOOTBLOCK_ADDR + * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE * | Unused hole | * | (86KiB) | * +--------------------------------+ -- cgit v1.2.3