From b2ea2f29b872d2c8d217f9a3794187a3125cde21 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Sat, 15 Jul 2023 00:28:31 +0200
Subject: soc/amd/genoa: Hook up BERT

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ie21bf8d436de19c23ae2176bf8d061564cd5b9cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
---
 src/soc/amd/genoa/Kconfig | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src')

diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index 28774cc9cd..592043eb8a 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -193,4 +193,20 @@ config ACPI_SSDT_PSD_INDEPENDENT
 	  cores to transition between p-states independently. A vendor may
 	  choose to generate _PSD object to allow cores to transition together.
 
+config ACPI_BERT
+	bool "Build ACPI BERT Table"
+	default y
+	depends on HAVE_ACPI_TABLES
+	help
+	  Report Machine Check errors identified in POST to the OS in an
+	  ACPI Boot Error Record Table.
+
+config ACPI_BERT_SIZE
+	hex
+	default 0x4000 if ACPI_BERT
+	default 0x0
+	help
+	  Specify the amount of DRAM reserved for gathering the data used to
+	  generate the ACPI table.
+
 endif # SOC_AMD_GENOA
-- 
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