From b256e6303c13abc13825bf2d3fb2fbc2ed1fd788 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 2 Aug 2024 12:44:19 +0530 Subject: mb/google/rex: Skip UART0 config in FSP UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=none TEST=Able to build and boot google/rex0. Able to see all debug prints over CPU uart. Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750 Reviewed-by: Eric Lai Reviewed-by: Dinesh Gehlot Tested-by: build bot (Jenkins) --- src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index 1a80e2aecb..00acbecc3e 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -73,7 +73,7 @@ chip soc/intel/meteorlake register "skip_ext_gfx_scan" = "1" register "serial_io_uart_mode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" -- cgit v1.2.3