From b203c2f95e8174bff1170a47d06186a315de4997 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Thu, 20 Aug 2009 14:48:03 +0000 Subject: 20090819-2-trim-down-cbfs: CBFS uses sprintf, which requires vtxprintf, which requires (in the current design) a nested function. That works on x86, but on PPC this requires a trampoline. In the ROM stage, this is not available, so remove the single use of sprintf and replace it with a direct string handler - it's only used to fill in fixed-length hex values. 20090819-3-more-noreturns-in-romcc: Mark two more functions in romcc as noreturn. Helps clang's scan-build a bit 20090819-4-cbfsify-ppc: Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and not complete yet. 20090819-5-fix-ppc-build: The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat plausible value. With fixes to tohex* functions as discussed on the list, and correct function names. Signed-off-by: Patrick Georgi Acked-by: Myles Watson Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/arch/i386/Config.lb | 1 - src/arch/ppc/Config.lb | 6 ++++++ src/arch/ppc/init/ppc_main.c | 20 ++++---------------- src/lib/cbfs.c | 18 ++++++++++++++++-- src/mainboard/embeddedplanet/ep405pc/Options.lb | 1 + .../motorola/sandpointx3_altimus_mpc7410/Options.lb | 4 ++-- src/mainboard/totalimpact/briq/Options.lb | 1 + 7 files changed, 30 insertions(+), 21 deletions(-) (limited to 'src') diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb index 4c6278acb5..380d05ba4d 100644 --- a/src/arch/i386/Config.lb +++ b/src/arch/i386/Config.lb @@ -13,7 +13,6 @@ if CONFIG_CBFS if CONFIG_USE_FAILOVER_IMAGE else initobject /src/lib/cbfs.o - initobject /src/console/vsprintf.o initobject /src/lib/lzma.o end end diff --git a/src/arch/ppc/Config.lb b/src/arch/ppc/Config.lb index 1a5ad840e7..aba64c1f98 100644 --- a/src/arch/ppc/Config.lb +++ b/src/arch/ppc/Config.lb @@ -1,3 +1,4 @@ +uses CONFIG_CBFS ldscript init/ldscript.lb makerule coreboot.strip @@ -10,6 +11,11 @@ makerule coreboot.rom action "cp $< $@" end +if CONFIG_CBFS + initobject /src/lib/cbfs.o + initobject /src/lib/lzma.o +end + dir init dir lib dir boot diff --git a/src/arch/ppc/init/ppc_main.c b/src/arch/ppc/init/ppc_main.c index 4dd4487ae8..150deeea67 100644 --- a/src/arch/ppc/init/ppc_main.c +++ b/src/arch/ppc/init/ppc_main.c @@ -5,12 +5,7 @@ #include #include - -extern unsigned _iseg[]; -extern unsigned _liseg[]; -extern unsigned _eliseg[]; - -void (*payload)(void) = (void (*)(void))_iseg; +#include /* * At this point we're running out of flash with our @@ -25,8 +20,7 @@ extern void flush_dcache(void); void ppc_main(void) { - unsigned *from; - unsigned *to; + void (*payload)(void); /* * very early board initialization @@ -49,15 +43,9 @@ void ppc_main(void) flush_dcache(); /* - * Relocate payload (text & data) if necessary + * Relocate payload (text & data) */ - if (_liseg != _iseg) { - from = _liseg; - to = _iseg; - while (from < _eliseg) - *to++ = *from++; - } - + payload = cbfs_load_stage("fallback/coreboot_ram"); payload(); /* NOT REACHED */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 5a8b5f7762..ad45ece95a 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -124,13 +124,27 @@ struct cbfs_stage *cbfs_find_file(const char *name, int type) return (void *) CBFS_SUBHEADER(file); } +static int tohex4(unsigned int c) +{ + return (c<=9)?(c+'0'):(c-10+'a'); +} + +static void tohex16(unsigned int val, char* dest) +{ + dest[0]=tohex4(val>>12); + dest[1]=tohex4((val>>8) & 0xf); + dest[2]=tohex4((val>>4) & 0xf); + dest[3]=tohex4(val & 0xf); +} + void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest) { - char name[17]; + char name[17]="pciXXXX,XXXX.rom"; struct cbfs_optionrom *orom; u8 *src; - sprintf(name,"pci%04x,%04x.rom", vendor, device); + tohex16(vendor, name+3); + tohex16(device, name+8); orom = (struct cbfs_optionrom *) cbfs_find_file(name, CBFS_TYPE_OPTIONROM); diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb index 9aa6a3d0f3..e91b12136b 100644 --- a/src/mainboard/embeddedplanet/ep405pc/Options.lb +++ b/src/mainboard/embeddedplanet/ep405pc/Options.lb @@ -106,6 +106,7 @@ default CONFIG_FS_FAT=1 default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz" default CONFIG_ROM_SIZE=1048576 +default CONFIG_ROM_IMAGE_SIZE=160*1024 ## Board has fixed size RAM default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024 diff --git a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb index 2ba981db7d..a4108ad111 100644 --- a/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb +++ b/src/mainboard/motorola/sandpointx3_altimus_mpc7410/Options.lb @@ -94,8 +94,8 @@ default CONFIG_FS_FAT=1 default CONFIG_AUTOBOOT_CMDLINE="hdc1:/vmlinuz" # coreboot must fit into 128KB -default CONFIG_ROM_IMAGE_SIZE=131072 -default CONFIG_ROM_SIZE={CONFIG_ROM_IMAGE_SIZE+CONFIG_PAYLOAD_SIZE} +default CONFIG_ROM_IMAGE_SIZE=160*1024 +default CONFIG_ROM_SIZE=384*1024 default CONFIG_PAYLOAD_SIZE=262144 # Set stack and heap sizes (stage 2) diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb index 8cc96d2914..b33efdd4a0 100644 --- a/src/mainboard/totalimpact/briq/Options.lb +++ b/src/mainboard/totalimpact/briq/Options.lb @@ -96,6 +96,7 @@ default CONFIG_IDE_OFFSET=0 # ROM is 1Mb default CONFIG_ROM_SIZE=1048576 +default CONFIG_ROM_IMAGE_SIZE=128*1024 # Set stack and heap sizes (stage 2) default CONFIG_STACK_SIZE=0x10000 -- cgit v1.2.3