From b04405ff766db9b4d0d6665b28d4860788fb6889 Mon Sep 17 00:00:00 2001 From: Zheng Bao Date: Tue, 19 Jan 2021 22:37:59 +0800 Subject: soc/amd/cezanne: Add UCODE firmware to CBFS Change-Id: I0de08b98e73c61db55ff994af00c84cf24273a98 Signed-off-by: Zheng Bao Reviewed-on: https://review.coreboot.org/c/coreboot/+/49684 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/soc/amd/cezanne/Kconfig | 1 + src/soc/amd/cezanne/Makefile.inc | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 9b766736f0..c34f127393 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -31,6 +31,7 @@ config SOC_SPECIFIC_OPTIONS select SSE2 select UDK_2017_BINDING select X86_AMD_FIXED_MTRRS + select SUPPORT_CPU_UCODE_IN_CBFS config CHIPSET_DEVICETREE string diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index ef099de593..bcf1d722c4 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -101,8 +101,6 @@ PSP_ELF_FILE=$(objcbfs)/bootblock.elf PSP_BIOSBIN_SIZE=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$5}') PSP_BIOSBIN_DEST=$(shell $(READELF_bootblock) -l $(PSP_ELF_FILE) | grep LOAD | awk '{print $$3}') -# type = 0x66 - # type = 0xb - See #55758 (NDA) for bit definitions. PSP_SOFTFUSE_BITS += 28 @@ -183,4 +181,6 @@ apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(CEZANNE_FWM_POSITION) apu/amdfw-type := raw +cpu_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/UcodePatch_*.bin) + endif # ($(CONFIG_SOC_AMD_CEZANNE),y) -- cgit v1.2.3