From afb926ab0ab1405cb89245970073704cc9d2af83 Mon Sep 17 00:00:00 2001 From: Anil Kumar Date: Wed, 26 Apr 2023 11:31:20 -0700 Subject: soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate when CSE FW sync is performed")' adds support to choose CSE FW update to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a dependency on ME_RW firmware compression. This patch removes the dependency between CSE FW sync in RAMSTAGE and ME_RW firmware compression as these two are not related and should be decoupled to support CSE FW sync in RAMSTAGE without the requirement to compress ME_FW. Signed-off-by: Anil Kumar Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796 Reviewed-by: Sridhar Siricilla Tested-by: build bot (Jenkins) Reviewed-by: Jérémy Compostella --- src/soc/intel/common/block/cse/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 73cb51bc7f..1eb3eff8f1 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -256,9 +256,8 @@ config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE bool default n - depends on SOC_INTEL_CSE_LITE_COMPRESS_ME_RW help - Use this option for CSE FW Update when compressed blobs are used. + Use this option if CSE RW update needs to be triggered during RAMSTAGE. config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT bool -- cgit v1.2.3