From af90a1e6afd93bb4c42393ebd9a47b21e2222737 Mon Sep 17 00:00:00 2001 From: Piotr Kleinschmidt Date: Thu, 21 May 2020 17:48:12 +0200 Subject: mb/pcengines/apu1/platform_cfg.h: Unset UsbRxMode to avoid platform reset issue MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On PC Engines apu1 there were issues with cold reset. Platform hangs in boot path after performing reset using CF9h. CB:10549 (amd/sb800: Make UsbRxMode per-board customizable) mentions a similar issue, and added a configuration macro for it. That error is also described in AMD SB800 Family Product Errata, section 15 USB Resets Asynchronously With Port CF9h Hard Reset. This workaround simply non-execute USB configuration during boot and hence no reset via CF9h is done. TEST=perform multiple cold resets and see if platform boots Signed-off-by: Piotr Kleinschmidt Change-Id: Ie6cebcfc4b77e121ef44a25fa81377eb5e1f0644 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41627 Reviewed-by: Michał Żygowski Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/pcengines/apu1/platform_cfg.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'src') diff --git a/src/mainboard/pcengines/apu1/platform_cfg.h b/src/mainboard/pcengines/apu1/platform_cfg.h index 2f5c56c0da..63a3d5a7cb 100644 --- a/src/mainboard/pcengines/apu1/platform_cfg.h +++ b/src/mainboard/pcengines/apu1/platform_cfg.h @@ -212,4 +212,18 @@ */ #define FADT_PM_PROFILE 1 +/** + * @def USB_RX_MODE + * 0x00 - leave Cg2Pll voltage at default value (1.222V) + * 0x01 - lower Cg2Pll voltage to 1.1V + * + * Workaround for reset issues via outb(0x6, 0xcf9). + * For details check: + * AMD SB800 Family Product Errata, + * Section 15. USB Resets Asynchronously With Port CF9h Hard Reset + * + */ + +#define USB_RX_MODE 0x00 + #endif /* _PLATFORM_CFG_H_ */ -- cgit v1.2.3