From ae7e7ccdc937a7a927a7d94bcb8540e617589f35 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 5 Sep 2017 10:58:07 -0700 Subject: mainboard/intel/cannonlake_rvp: enable SATA Set sata enable FSP parameters. Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/21407 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 4 ++++ src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index baf951015e..119af485ac 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -28,6 +28,10 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + register "SataEnable" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 7f3e7a5f14..6e7c5359d6 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -28,6 +28,10 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + register "SataEnable" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3