From adec2e6c45fdbf3f2e1d7cde06ed09d00e6c6dff Mon Sep 17 00:00:00 2001 From: "Chris.Wang" Date: Wed, 4 Jan 2023 10:15:00 +0800 Subject: mb/google/skyrim/var/winterhold: set dxio_tx_vboost_enable for whiterun Turn on the dxio_tx_vboost_enable for winterhold/whiterun in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259622787 BRANCH=none TEST=confirm the setting has been set correspondingly with checking the FSP log. Signed-off-by: Chris.Wang Change-Id: I6aad3d9118180d2ffdfba38abc80b175b6f103bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71647 Reviewed-by: Jason Glenesk Tested-by: build bot (Jenkins) Reviewed-by: Dtrain Hsu --- src/mainboard/google/skyrim/variants/winterhold/overridetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src') diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 1d50bd5b0b..b4e7c467f5 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -99,6 +99,9 @@ chip soc/amd/mendocino register "stt_skin_temp_apu_F" = "0x3200" device domain 0 on + + register "dxio_tx_vboost_enable" = "1" + device ref gpp_bridge_1 on # Required so the NVMe gets placed into D3 when entering S0i3. chip drivers/pcie/rtd3/device -- cgit v1.2.3