From ac435b4b911212598ce70092ce5c67a21a9f1111 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 15 Nov 2022 14:00:22 +0200 Subject: intel/haswell,lynxpoint: Fix out() parameter order MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ife134ef6d508113e3cd27b6352ee5044aee43744 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/69677 Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Angel Pons Reviewed-by: Nico Huber --- src/northbridge/intel/haswell/gma.c | 2 +- src/southbridge/intel/lynxpoint/pmutil.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index e1b8b73097..6e6948b70f 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -408,7 +408,7 @@ static void gma_enable_swsci(void) /* Clear DMISCI status */ reg16 = inw(get_pmbase() + TCO1_STS); reg16 &= DMISCI_STS; - outw(get_pmbase() + TCO1_STS, reg16); + outw(reg16, get_pmbase() + TCO1_STS); /* Clear and enable ACPI TCO SCI */ enable_tco_sci(); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 8117b4d3ea..dd7f1990b9 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -356,7 +356,7 @@ void enable_tco_sci(void) u16 gpe0_sts = pch_is_lp() ? LP_GPE0_STS_4 : GPE0_STS; /* Clear pending events */ - outl(get_pmbase() + gpe0_sts, TCOSCI_STS); + outl(TCOSCI_STS, get_pmbase() + gpe0_sts); /* Enable TCO SCI events */ enable_gpe(TCOSCI_EN); -- cgit v1.2.3