From aaa4a0d39e438b0a3b60e673f6375d5048cafbc5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 26 Jan 2021 17:31:48 +0100 Subject: cpu/intel/common/fsb.c: Add Broadwell CPUID models Like Haswell, Broadwell has a "FSB" speed of 100 MHz. Add the IDs for both the traditional and ULT variants of Broadwell, because the CPU driver for Haswell already contains CPUIDs for both Broadwell types. Without this patch, Broadwell CPUs would hang when trying to print the first console log message, but only if flashconsole was not enabled. This was missed in commit f542b7bcef (cpu/intel/haswell: Add Broadwell CPUIDs and microcode) and went unnoticed until now because the tests were done with flashconsole enabled, which somehow boots properly even though the console time tracking would not work (depends on TSC). Tested on out-of-tree Acer E5-573, fixes booting without flashconsole. Change-Id: I78a1696771d4d6d2138ec432dc0d8e030f14293b Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/49939 Reviewed-by: Matt DeVillier Reviewed-by: Patrick Rudolph Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/cpu/intel/common/fsb.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src') diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 3d46bbc4b9..68abe1c875 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -44,8 +44,10 @@ static int get_fsb_tsc(int *fsb, int *ratio) case 0x2a: /* SandyBridge BCLK fixed at 100MHz */ case 0x3a: /* IvyBridge BCLK fixed at 100MHz */ case 0x3c: /* Haswell BCLK fixed at 100MHz */ + case 0x3d: /* Broadwell-ULT BCLK fixed at 100MHz */ case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */ case 0x46: /* Haswell-GT3e BCLK fixed at 100MHz */ + case 0x47: /* Broadwell BCLK fixed at 100MHz */ *fsb = 100; *ratio = (rdmsr(MSR_PLATFORM_INFO).lo >> 8) & 0xff; break; -- cgit v1.2.3