From aaa16fede70aaac56d1c835e663f52c4735826d8 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Fri, 1 Sep 2017 19:55:49 -0400 Subject: superio/winbond/*: Unify w*_set_clksel_48() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Kyösti Mälkki Reviewed-by: Paul Menzel --- src/mainboard/advansus/a785e-i/romstage.c | 2 +- src/mainboard/avalue/eax-785e/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/msi/ms6178/romstage.c | 2 +- src/mainboard/supermicro/h8dme/romstage.c | 2 +- src/mainboard/supermicro/h8dmr/romstage.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/winent/pl6064/romstage.c | 2 +- src/mainboard/winnet/g170/romstage.c | 2 +- src/superio/winbond/Makefile.inc | 2 +- src/superio/winbond/common/early_init.c | 92 +++++++++++++++++++++++++ src/superio/winbond/common/early_serial.c | 81 ---------------------- src/superio/winbond/common/winbond.h | 1 + 16 files changed, 106 insertions(+), 94 deletions(-) create mode 100644 src/superio/winbond/common/early_init.c delete mode 100644 src/superio/winbond/common/early_serial.c (limited to 'src') diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index d143724808..7714f72fe2 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb800_clk_output_48Mhz(); - w83627hf_set_clksel_48(PNP_DEV(0x2e, 0)); + winbond_set_clksel_48(PNP_DEV(0x2e, 0)); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index d32e7b253d..e574ecdcb0 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -100,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb800_clk_output_48Mhz(); - w83627hf_set_clksel_48(CLK_DEV); + winbond_set_clksel_48(CLK_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 4ba528c069..0703ba6348 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -78,7 +78,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - w83697hf_set_clksel_48(SERIAL_DEV); + winbond_set_clksel_48(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index d7cbc32163..2f1180e96f 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -33,7 +33,7 @@ void mainboard_romstage_entry(unsigned long bist) { - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index cacdd41b77..9deb940c4e 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 550bb8925a..9da1ab50ed 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index eb6edff249..7ba4f60241 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -130,7 +130,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index edede81c09..3c255c5228 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 220098dadd..3731e8852f 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -53,7 +53,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) report_bist_failure(bist); sb7xx_51xx_enable_wideio(0, 0x1600); /* though UARTs are on the NUVOTON BMC */ - w83627dhg_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); sb7xx_51xx_disable_wideio(0); post_code(0x34); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 2f8eccefa2..faf87c7a1b 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -378,7 +378,7 @@ void main(unsigned long bist) */ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); /* EmbedComInit(); */ - w83697hf_set_clksel_48(DUMMY_DEV); + winbond_set_clksel_48(DUMMY_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* enable_vx800_serial(); */ diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 624163b806..a8f64cf35c 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -59,7 +59,7 @@ void asmlinkage mainboard_romstage_entry(unsigned long bist) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_set_clksel_48(SERIAL_DEV); + winbond_set_clksel_48(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/winnet/g170/romstage.c b/src/mainboard/winnet/g170/romstage.c index 4ba528c069..0703ba6348 100644 --- a/src/mainboard/winnet/g170/romstage.c +++ b/src/mainboard/winnet/g170/romstage.c @@ -78,7 +78,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - w83697hf_set_clksel_48(SERIAL_DEV); + winbond_set_clksel_48(SERIAL_DEV); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index ae4b283d3c..b0b7b8c520 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -14,7 +14,7 @@ ## ## include generic winbond pre-ram stage driver -romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_serial.c +romstage-$(CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE) += common/early_init.c subdirs-y += w83627dhg subdirs-y += w83627ehg diff --git a/src/superio/winbond/common/early_init.c b/src/superio/winbond/common/early_init.c new file mode 100644 index 0000000000..7c3ce2b3a5 --- /dev/null +++ b/src/superio/winbond/common/early_init.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * A generic romstage (pre-ram) driver for various Winbond Super I/O chips. + * + * The following is derived directly from the vendor Winbond's data-sheets: + * + * To toggle between `configuration mode` and `normal operation mode` as to + * manipulation the various LDN's in Winbond Super I/O's we are required to + * pass magic numbers `passwords keys`. + * + * WINBOUND_ENTRY_KEY := enable configuration : 0x87 + * WINBOUND_EXIT_KEY := disable configuration : 0xAA + * + * To modify a LDN's configuration register, we use the index port to select + * the index of the LDN and then write to the data port to alter the + * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a + * user modified pair is 0x2E, 0x2F respectively. + * + */ + +#include +#include +#include +#include "winbond.h" + +#define WINBOND_ENTRY_KEY 0x87 +#define WINBOND_EXIT_KEY 0xAA + +/* Enable configuration: pass entry key '0x87' into index port dev. */ +void pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(WINBOND_ENTRY_KEY, port); + outb(WINBOND_ENTRY_KEY, port); +} + +/* Disable configuration: pass exit key '0xAA' into index port dev. */ +void pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(WINBOND_EXIT_KEY, port); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} + +void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state) +{ + uint8_t byte; + + /* Configure pin mux */ + pnp_enter_conf_state(dev); + byte = pnp_read_config(dev, offset); + byte &= ~mask; + byte |= state; + pnp_write_config(dev, offset, byte); + pnp_exit_conf_state(dev); +} + +void winbond_set_clksel_48(pnp_devfn_t dev) +{ + u8 reg8; + + pnp_enter_conf_state(dev); + reg8 = pnp_read_config(dev, 0x24); + reg8 |= (1 << 6); /* Set the clock input to 48MHz. */ + pnp_write_config(dev, 0x24, reg8); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c deleted file mode 100644 index aebbd38b46..0000000000 --- a/src/superio/winbond/common/early_serial.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* - * A generic romstage (pre-ram) driver for Winbond variant Super I/O chips. - * - * The following is derived directly from the vendor Winbond's data-sheets: - * - * To toggle between `configuration mode` and `normal operation mode` as to - * manipulation the various LDN's in Winbond Super I/O's we are required to - * pass magic numbers `passwords keys`. - * - * WINBOUND_ENTRY_KEY := enable configuration : 0x87 - * WINBOUND_EXIT_KEY := disable configuration : 0xAA - * - * To modify a LDN's configuration register, we use the index port to select - * the index of the LDN and then write to the data port to alter the - * parameters. A default index, data port pair is 0x4E, 0x4F respectively, a - * user modified pair is 0x2E, 0x2F respectively. - * - */ - -#include -#include -#include -#include "winbond.h" - -#define WINBOND_ENTRY_KEY 0x87 -#define WINBOND_EXIT_KEY 0xAA - -/* Enable configuration: pass entry key '0x87' into index port dev. */ -void pnp_enter_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(WINBOND_ENTRY_KEY, port); - outb(WINBOND_ENTRY_KEY, port); -} - -/* Disable configuration: pass exit key '0xAA' into index port dev. */ -void pnp_exit_conf_state(pnp_devfn_t dev) -{ - u16 port = dev >> 8; - outb(WINBOND_EXIT_KEY, port); -} - -/* Bring up early serial debugging output before the RAM is initialized. */ -void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) -{ - pnp_enter_conf_state(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); -} - -void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state) -{ - uint8_t byte; - - /* Configure pin mux */ - pnp_enter_conf_state(dev); - byte = pnp_read_config(dev, offset); - byte &= ~mask; - byte |= state; - pnp_write_config(dev, offset, byte); - pnp_exit_conf_state(dev); -} diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 6e67eeb83d..e472018bf1 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -22,6 +22,7 @@ void winbond_enable_serial(pnp_devfn_t dev, uint16_t iobase); void winbond_set_pinmux(pnp_devfn_t dev, uint8_t offset, uint8_t mask, uint8_t state); +void winbond_set_clksel_48(pnp_devfn_t dev); void pnp_enter_conf_state(pnp_devfn_t dev); void pnp_exit_conf_state(pnp_devfn_t dev); -- cgit v1.2.3