From aa7cf5597b0f4d59c5d7fe42a8b5130852056bff Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 3 Jun 2018 10:44:55 +0200 Subject: nb/intel/pineview: Switch to POSTCAR_STAGE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: If23925e2837645c974e4094e7e2d90e700d3d9e8 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/26786 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/cpu/intel/socket_FCBGA559/Makefile.inc | 5 +---- src/northbridge/intel/pineview/Kconfig | 2 ++ src/northbridge/intel/pineview/Makefile.inc | 2 ++ src/northbridge/intel/pineview/ram_calc.c | 14 +++++++------- 4 files changed, 12 insertions(+), 11 deletions(-) (limited to 'src') diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 7c37019194..7993294a17 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -8,10 +8,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc -else cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif + romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index e8ef9d9403..80f566acb6 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -29,6 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT select RELOCATABLE_RAMSTAGE select INTEL_GMA_ACPI + select POSTCAR_STAGE + select POSTCAR_CONSOLE config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc index a4c08c8af1..d7936c1fbf 100644 --- a/src/northbridge/intel/pineview/Makefile.inc +++ b/src/northbridge/intel/pineview/Makefile.inc @@ -25,4 +25,6 @@ romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c index fd893bc87a..d116709cd9 100644 --- a/src/northbridge/intel/pineview/ram_calc.c +++ b/src/northbridge/intel/pineview/ram_calc.c @@ -107,9 +107,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -132,8 +133,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } -- cgit v1.2.3