From a5215c4eb3a4cbe0ef32257c4da2e5a6e0febdef Mon Sep 17 00:00:00 2001 From: Reka Norman Date: Fri, 22 Sep 2023 15:26:54 +1000 Subject: soc/intel: Move USB wake methods to a common ASL file The ACPI methods for enabling USB wake are identical on ADL, CNL and SKL. Move them to a common ASL file so they can be reused more easily on other SoCs. Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks in devicetree to a common header. BUG=b:300844110 TEST=Use abuild to build kinox, puff, and fizz with and without this change. Check the generated dsdt.aml is unchanged. Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce Signed-off-by: Reka Norman Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth --- src/soc/intel/alderlake/acpi/xhci.asl | 47 +-------------------- src/soc/intel/alderlake/chip.h | 1 + src/soc/intel/alderlake/include/soc/usb.h | 7 ---- src/soc/intel/cannonlake/acpi/xhci.asl | 47 +-------------------- src/soc/intel/cannonlake/chip.h | 1 + src/soc/intel/cannonlake/include/soc/usb.h | 7 ---- src/soc/intel/common/acpi/xhci_wake.asl | 49 ++++++++++++++++++++++ .../intel/common/block/include/intelblocks/xhci.h | 7 ++++ src/soc/intel/skylake/acpi/xhci.asl | 47 +-------------------- src/soc/intel/skylake/chip.h | 1 + src/soc/intel/skylake/include/soc/usb.h | 7 ---- 11 files changed, 65 insertions(+), 156 deletions(-) create mode 100644 src/soc/intel/common/acpi/xhci_wake.asl (limited to 'src') diff --git a/src/soc/intel/alderlake/acpi/xhci.asl b/src/soc/intel/alderlake/acpi/xhci.asl index e4001fe8c2..1c3bbbe2da 100644 --- a/src/soc/intel/alderlake/acpi/xhci.asl +++ b/src/soc/intel/alderlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include #include -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 &= PORTSCN_BITS_OFF_MASK - Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 &= (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include /* XHCI Controller 0:14.0 */ diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 65d6e85cb0..b1e90fa774 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h index 2a701c8cc2..b84cce7a66 100644 --- a/src/soc/intel/alderlake/include/soc/usb.h +++ b/src/soc/intel/alderlake/include/soc/usb.h @@ -163,11 +163,4 @@ struct tcss_port_config { .ocpin = (pin), \ } -/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif diff --git a/src/soc/intel/cannonlake/acpi/xhci.asl b/src/soc/intel/cannonlake/acpi/xhci.asl index 0f8f51fe20..beaa843911 100644 --- a/src/soc/intel/cannonlake/acpi/xhci.asl +++ b/src/soc/intel/cannonlake/acpi/xhci.asl @@ -3,51 +3,8 @@ #include #include -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 = Local0 & PORTSCN_BITS_OFF_MASK - Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 = Local0 & (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include /* XHCI Controller 0:14.0 */ diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 30930502c1..994f2aebef 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h index 20b3149dd7..3f020ef7c1 100644 --- a/src/soc/intel/cannonlake/include/soc/usb.h +++ b/src/soc/intel/cannonlake/include/soc/usb.h @@ -186,11 +186,4 @@ struct usb3_port_config { .gen2_rx_filter_sel = 0x44, \ } -/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif diff --git a/src/soc/intel/common/acpi/xhci_wake.asl b/src/soc/intel/common/acpi/xhci_wake.asl new file mode 100644 index 0000000000..e029a6f05c --- /dev/null +++ b/src/soc/intel/common/acpi/xhci_wake.asl @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + Local0 = Arg1 + ((Arg0 - 1) * 0x10) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) + Field (PSCR, DWordAcc, NoLock, Preserve) + { + PSCT, 32, + } + Local0 = PSCT + Local0 &= PORTSCN_BITS_OFF_MASK + Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE + PSCT = Local0 +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Local0 = Arg0 + + While (1) { + FindSetRightBit (Local0, Local1) + If (Local1 == 0) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + */ + Local0 &= (Local0 - 1) + } +} diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h index 15b16d2073..1a72e0fee8 100644 --- a/src/soc/intel/common/block/include/intelblocks/xhci.h +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -16,6 +16,13 @@ #define PORTSCN_BITS_OFF_MASK ~0x80FE0012 #define PORTSCXUSB3_OFFSET 0x540 +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) + #if !defined(__ACPI__) #include #include diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 0540919e37..bfe6c6df77 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -2,51 +2,8 @@ #include -/* - * USB Port Wake Enable (UPWE) on usb attach/detach - * Arg0 - Port Number - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UPWE, 3, Serialized) -{ - Local0 = Arg1 + ((Arg0 - 1) * 0x10) - - /* Map ((XMEM << 16) + Local0 in PSCR */ - OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10) - Field (PSCR, DWordAcc, NoLock, Preserve) - { - PSCT, 32, - } - Local0 = PSCT - Local0 = Local0 & PORTSCN_BITS_OFF_MASK - Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE - PSCT = Local0 -} - -/* - * USB Wake Enable Setup (UWES) - * Arg0 - Port enable bitmap - * Arg1 - Port 1 Status and control offset - * Arg2 - xHCI Memory-mapped address - */ -Method (UWES, 3, Serialized) -{ - Local0 = Arg0 - - While (1) { - FindSetRightBit (Local0, Local1) - If (Local1 == 0) { - Break - } - UPWE (Local1, Arg1, Arg2) - /* - * Clear the lowest set bit in Local0 since it was - * processed. - */ - Local0 = Local0 & (Local0 - 1) - } -} +/* Include UWES method for enabling USB wake */ +#include /* XHCI Controller 0:14.0 */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 5119037f6a..3070c462ba 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index 79126037c5..612ad5fa2e 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -180,11 +180,4 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } -/* - * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds - * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to - * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. - */ -#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1)) - #endif -- cgit v1.2.3