From a41991a3f91987c04c2c80f271d9e63d32ca4338 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 3 Nov 2020 13:05:04 -0600 Subject: mb/purism/librem_mini: Increase TDP/PL2 setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PL2 was set artificially low during development when the active cooling fan was not functional, and never corrected once the fan was fixed. Raise PL2 to a value which works with both Librem Mini variants. Change-Id: Ie377392020f73359aed80ddae727adb6f8d06344 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47186 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner --- src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 308fa69489..9d2b34b16c 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -8,7 +8,7 @@ chip soc/intel/cannonlake # Power limit register "power_limits_config" = "{ .tdp_pl1_override = 25, - .tdp_pl2_override = 28, + .tdp_pl2_override = 51, }" # Enable Enhanced Intel SpeedStep -- cgit v1.2.3