From a405a5860d2765911fe7655e81c78e3b563bacab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 2 Mar 2017 13:01:58 +0200 Subject: Stage rules.h: Add ENV_LIBAGESA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Definition is required to enable use of printk() from AGESA proper. Change-Id: I6666a003c91794490f670802d496321ffb965cd3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/18544 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/include/rules.h | 23 ++++++++++++++++++++--- src/vendorcode/amd/agesa/Makefile.inc | 1 + 2 files changed, 21 insertions(+), 3 deletions(-) (limited to 'src') diff --git a/src/include/rules.h b/src/include/rules.h index a6328049ed..0f212318a6 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -27,6 +27,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "bootblock" #elif defined(__ROMSTAGE__) @@ -37,6 +38,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "romstage" #elif defined(__SMM__) @@ -47,6 +49,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "smm" #elif defined(__VERSTAGE__) @@ -57,6 +60,7 @@ #define ENV_VERSTAGE 1 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "verstage" #elif defined(__RAMSTAGE__) @@ -67,6 +71,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "ramstage" #elif defined(__RMODULE__) @@ -77,6 +82,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 1 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "rmodule" #elif defined(__POSTCAR__) @@ -87,14 +93,24 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 1 +#define ENV_LIBAGESA 0 #define ENV_STRING "postcar" +#elif defined(__LIBAGESA__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 +#define ENV_POSTCAR 0 +#define ENV_LIBAGESA 1 +#define ENV_STRING "libagesa" + #else /* * Default case of nothing set for random blob generation using - * create_class_compiler that isn't bound to a stage. Also AGESA - * apparently builds things compeletely separate from coreboot's - * build infrastructure -- hardcoding its own rules. + * create_class_compiler that isn't bound to a stage. */ #define ENV_BOOTBLOCK 0 #define ENV_ROMSTAGE 0 @@ -103,6 +119,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "UNKNOWN" #endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index fab6f63613..f2423d0718 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -12,6 +12,7 @@ subdirs-y += common classes-y += libagesa libagesa-y = +libagesa-generic-ccopts += -D__LIBAGESA__ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) -- cgit v1.2.3