From a2cf34129fb3b2a9302bb7cf06e4ee758b9bb85a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 4 May 2021 23:36:36 +0530 Subject: include/console: Align ramstage Boot State Machine postcodes This patch ensures all boot state machine postcodes are in right order. Move POST_ENTRY_RAMSTAGE macro definition after POST_BS_PAYLOAD_BOOT. Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/include/console/post_codes.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src') diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h index ee74dcb23e..677cd36545 100644 --- a/src/include/console/post_codes.h +++ b/src/include/console/post_codes.h @@ -181,14 +181,6 @@ */ #define POST_PRE_HARDWAREMAIN 0x79 -/** - * \brief Entry into coreboot in RAM stage main() - * - * This is the first call in hardwaremain.c. If this code is POSTed, then - * ramstage has successfully loaded and started executing. - */ -#define POST_ENTRY_RAMSTAGE 0x80 - /** * \brief Load Payload * @@ -203,6 +195,14 @@ */ #define POST_BS_PAYLOAD_BOOT 0x7b +/** + * \brief Entry into coreboot in RAM stage main() + * + * This is the first call in hardwaremain.c. If this code is POSTed, then + * ramstage has successfully loaded and started executing. + */ +#define POST_ENTRY_RAMSTAGE 0x80 + /** * \brief Before calling FSP Notify before End of Firmware * -- cgit v1.2.3