From a27d1fa175a814f32ada7b82144ff54ffdf7e654 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 11 Jan 2022 16:43:46 +0100 Subject: soc/amd/sabrina/include/aoac_defs: add additional UARTs Compared to Cezanne there are 3 more UARTs controllers. Signed-off-by: Felix Held Change-Id: Id98767197a21cb1a61f54fc9b256b10a9506c791 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61082 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/sabrina/include/soc/aoac_defs.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/amd/sabrina/include/soc/aoac_defs.h b/src/soc/amd/sabrina/include/soc/aoac_defs.h index 7554aa6c33..4b2b4fe580 100644 --- a/src/soc/amd/sabrina/include/soc/aoac_defs.h +++ b/src/soc/amd/sabrina/include/soc/aoac_defs.h @@ -1,7 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -/* TODO: Check if this is still correct */ - #ifndef AMD_SABRINA_AOAC_DEFS_H #define AMD_SABRINA_AOAC_DEFS_H @@ -15,7 +13,10 @@ #define FCH_AOAC_DEV_I2C5 10 #define FCH_AOAC_DEV_UART0 11 #define FCH_AOAC_DEV_UART1 12 +#define FCH_AOAC_DEV_UART2 16 #define FCH_AOAC_DEV_AMBA 17 +#define FCH_AOAC_DEV_UART4 20 +#define FCH_AOAC_DEV_UART3 26 #define FCH_AOAC_DEV_ESPI 27 #define FCH_AOAC_DEV_EMMC 28 -- cgit v1.2.3