From a2389ef3162be930e576af68e613d54ef4884cd4 Mon Sep 17 00:00:00 2001 From: Elyes Haouas Date: Sat, 3 Dec 2022 13:27:54 +0100 Subject: nb/intel/x4x: Use read32p() Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082 Signed-off-by: Elyes Haouas Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/northbridge/intel/x4x/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src') diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 80375a75ff..71a0609e55 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -21,7 +21,7 @@ static uint32_t encode_pciexbar_length(void) void bootblock_early_northbridge_init(void) { /* Disable LaGrande Technology (LT) */ - read32((void *)TPM_BASE_ADDRESS); + read32p(TPM_BASE_ADDRESS); const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); -- cgit v1.2.3